Text version of the page

Datasheet

PrimeRail - 33951 PrimeRail

Overview PrimeRail is a full-chip power network analysis solution for low power and high performance designs at 90-nanometer (nm) and below. PrimeRail offers gate-level and transistor-level static and dynamic voltage-drop and electromigration (EM) analysis during implementation and sign-off. PrimeRail is the power network extension to Synopsys’ industry-leading sign-off solution in the Galaxy

™

Design Platform. Built on gold standards Star-RCXT

™

extraction and PrimeTime

®

sign-off technologies, PrimeRail delivers the highest accuracy, performance and capacity advantage. PrimeRail’s integration with the Galaxy Design Platform allows designers to achieve fast design convergence and a predictable path to sign-off.

Key Features and Benefits

PrimeTime

Full-chip static and dynamic power network sign-off for gates and transistors Multi-mode analysis of advanced low power designs using multiple voltage islands and multi-threshold-CMOS (MT-CMOS) / power-gating cells Fast and accurate dynamic modeling for memories, analog, custom IP Leading performance and capacity for multi-million gate system-on-chip (SoC) designs Proven accuracy – within 5% of HSPICE

STA and Delay Calculation Star-RCXT
Variation-aware (VX)ParasiticExtraction PrimeTime SI
Integrated Xtalk delay and noise analys is PrimeTime PX PrimeRail
Integrated gate-level power analysis Rail Analysis PrimeTime VX
Integrated variation-aware STA NanoTime Liberty CCS
Unified timing, SI, power and variation models NEWNEWNEW NEW Transistor-levelSTA and SI Binary SPEFVariation-awarePeak PowerIR DropModel GenerationSDC ®

Galaxy Design Platform integration for productive and predictable designFlexible analysis throughout the flow – voltage-drop prediction during design planning, pre-layout analysis and final sign-offLiberty

Figure 1: Synopsys’ sign-off solution in Galaxy Design Platform

Integration with PrimeTime tool for concurrent static timing analysis (STA), signal integrity (SI) and voltage-drop sign-off ECO fix for voltage-drop using decoupling capacitances “What-if” analysis for debug and optimization, esp. decoupling capacitance Vs voltage-drop Vs leakage trade-offs Detailed reporting and graphical user interface for pin-pointing hot spots TSMC Reference Flow 7.0 certified •••• •

™

Composite Current Source (CCS) Power library supportBuilt-in library characterization utility for dynamic current waveformsEmbedded full-chip parasitic extraction System and package RLC support Vector-free and vector-based dynamic analysis •••• ••—•—•• •