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Datasheet

Power Compiler - 33951 Power Compiler Automatic Power Management within Galaxy

™

Design Platform

Overview

Reducing power consumption is required in today’s semiconductor designs. Silicon technology advances have made it possible to pack millions of transistors switching at high clock speeds on a single chip. While these advances bring unprecedented performance to electronic products, they pose difficult power dissipation and distribution problems. These problems must be addressed, because consumers demand longer battery life in addition to lower cost in computers, battery-operated systems, medical devices, telecommunications equipment and many high-volume consumer products.

Power Compiler: Gate-Level Power Optimization At the gate level, Power Compiler delivers further push-button power reduction. It delivers an average of 10 to 20 percent reduction in power during gate-level optimization without violating timing constraints. Based on the user’s timing, power and area constraints, Power Compiler measures trade-offs between positive timing slacks, area and power and then delivers the lowest- power-consuming design that meets timing constraints, while maintaining the area limit when specified by the user. The push-button power optimization at the gate level reduces the dynamic power as well as the leakage power, which is the majority of the power consumed when the device is in standby mode. Power Compiler shares the same GUI, shell, and compile commands with Design Compiler and Physical Compiler. It is fully integrated with Design Compiler and the existing design flow. Power Management A key to successful power management is automatic power reduction. This enables designers to meet their power budgets without adversely affecting their productivity or time to market. Power Compiler’s push-button power reduction capabilities at the Register Transfer Level (RTL) and gate level are fully inte- grated with Synopsys’ Galaxy
™ design synthesis and physical design flow. Power Compiler Power Compiler
™ automatically minimizes power consumption at the RTL and gate level. At the RTL, during the design elabora- tion phase, Power Compiler performs automatic clock gating to reduce the power consumption. At the gate level, driven by the design constraints, it performs simultaneous optimization for timing, power and area. It supports multithreshold libraries for automatic leakage power optimization. Power Compiler is seamlessly integrated with the synthesis design flow and shares the same GUI, commands, constraints and libraries with the Design Compiler
® and Physical Compiler
® tools. Power Compiler: RTL Power Optimization Synopsys’ Power Compiler performs automatic clock gating at the RTL without requiring any changes to the RTL source. This enables fast and easy trade-off analysis and maintains technol- ogy-independent RTL source. Clock gating is a common power reduction technique used manually in many power-critical designs. Power Compiler’s clock gating is complementary to manual clock gating done at the block level. It gates the clocks of individual synchronous load-enable register banks instead of circulating the output back to the input when the load-enable condition is invalid. Power Compiler automates this technique during the design elaboration phase, without requiring any additional effort from the design engineer. When applicable, substantial power savings can be achieved — up to 70 percent or more — at the block level.