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Power Compiler

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int I
sw C
load

af=ab+c(b+d)Function: f=ab+bc+cdf=b(a+c)+cd

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Gn(Gate)(Subthreshold)

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Dynamic Power Leakage Power Switching Power - Load Capacitance Charge/DischargeInternal Power - Short Circuit between Power and Ground during transition Gate LeakageSubthreshold Leakage

For a complete directory of Synopsys’ available Power Solutions visit: www.synopsys.com/galaxypower.

High ActivityLow Activity Figure 2: Factoring technique for reducing the circuit switching activity.Figure 3: Power dissipation in CMOS designs.

Synopsys Advantage The Synopsys Power Management Solution for the design flow gives designers a powerful arsenal of tools to optimize, estimate, analyze and manage today’s shrinking power budgets. Design engineers who are serious about providing power-efficient, cutting-edge technology to their customers will easily see the value in handling power problems early in the flow. By under- standing a design’s power requirements at every phase of the design cycle, engineers will be able to produce high-perfor- mance, power-sensitive products without impacting cost or time to market. Synopsys, Inc.700 East Middlefield Road Mountain View, CA 94043www.synopsys.com

©2007 Synopsys, Inc. Synopsys, the Synopsys logo, Design Compiler and Physical Compiler are registered trademarks of Synopsys, Inc.Galaxy and Power Complier are trademarks of Synopsys, Inc. All other products or service names mentioned herein are trademarks of their respective holders and should be treated as such. Printed in the U.S.A. ©2007 Synopsys, Inc. 02/07.PS.WO.07-15161