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Design software, Integrated circuit core, ASIC, SRAM, Integrated circuit
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| IC Compiler The next-generation physical design system | |||||||||||||||||||||||||||||||||||||||
| Overview IC Compiler is an integral part of the Synopsys Galaxy™ Design Platform that delivers a complete design solution, including synthesis, physical implementation, low-power design, and design for manufacturability (DFM). IC Compiler is a single, convergent, chip-level physical implementation tool that includes flat and hierarchical design planning, placement and optimization, clock tree synthesis, routing, DFM, and low-power capabilities that enable de—signers to implement today's high-performance, complex designs. Widely adopted and recognized as the industry standard for physical implementation, IC Compiler provides best-in-class quality of results (QoR), strong sign-off correlation, and powerful DFM capabilities. • IC Compiler uses Extended Physical Synthesis (XPS), a significant capability that extends physical synthesis to full place-and-route. XPS enables faster turnaround time (TAT) as well as better QoR, measured in terms of the complete cost vector - timing, area, power, signal integrity, routability, and yield. • IC Compiler is tightly correlated to the industry-standard sign-off solutions-PrimeTime® SI and Star-RCXT™. Additionally, it utilizes these sign-off engines to achieve fast, accurate sign-off driven design closure during the final changes of physical design implementation. Sign-off driven design closure further increases design predictability. • IC Compiler provides a comprehensive DFM solution that concurrently optimizes for yield with timing, area, power, test, and routability. IC Compiler increases manufacturability of the design, optimizing both functional and parametric yield. • IC Compiler with concurrent hierarchical design enables powerful design planning and chip-level analysis features to handle large, complex designs. Providing early analysis and feasibility exploration, IC Compiler delivers smaller die size and achieves predictable design closure to reduce the cost of design. • IC Compiler with Zroute technology utilizes advanced routing algorithms, concurrent DFM optimizations and multi- | |||||||||||||||||||||||||||||||||||||||
| threading to deliver a combined speed increase of more | ian 10X in routing. | ||||||||||||||||||||||||||||||||||||||
| Benefits QoR XPS is an innovative technology in IC Compiler that unifies synthesis, placement, clock tree synthesis, and routing to deliver increased QoR, measured in terms of the complete cost vector - timing, area, power, signal integrity, routability, and yield. New technologies like concurrent multi-corner multi-mode (MCMM) optimization, enhanced signal integrity capabilities, and physical datapath enable designers to meet aggressive QoR targets for large, complex chips. Turnaround Time IC Compiler provides the fastest path to results. This is achieved using powerful design planning capabilities, complete convergence throughout the design stages, and a seamless RTL-to-GDSII flow. | |||||||||||||||||||||||||||||||||||||||
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| _____/T'hysicarN_____ 'PhysicarS--..EEL--Y^esigrr> s.Powe^X \Planning, 7^ Concurrent \ Optimization J | |||||||||||||||||||||||||||||||||||||||
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| GDSII | |||||||||||||||||||||||||||||||||||||||
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