IC Compiler - Synopsys - #6

• Ease of Use

— Core commands for placement, CTS, and routing

— Tel support throughout

— GUI

• Powerful features enable design analysis, visualization, debugging, and fixing

• Cross-referencing between logic vs. physical analysis

• Clock tree synthesis skew and latency analysis

• Hierarchical clock tree browser

• Power Network Analysis (PNA)

• Visual maps for Worst Negative Slack (WNS)/ congestion/cell density/scan/leakage power/dynamic power/total power and more

• Critical Area Analysis (CAA)

• CMP thickness and CMP hot spots

• Fast physical data analysis and editing

• PrimeTime-style analysis (path inspector) Interfaces

• Library Interface

— Reads LIB synthesis library containing functionality, timing, and design rule constraints

— Reads Milkyway (MWY) physical library describing technology and cell outlines

— Reads LEF, Technology File (TF) format

Inputs

— Verilog netlist

— SDC, DEF, SPEF, SBPF

— Several user-level commands are provided for specifying and modifying the floorplan

Outputs

— Verilog netlist

— SDC, DEF, SPEF, SBPF

— GDSII

User Interfaces

— Tel or GUI-based user interface

— All Design Compiler reports enhanced with physical -information; additional reports and commands enable analyzing layout and checking consistency of libraries and input flies

Supported Platforms

— AMD64, Sparc64, Linux32 4.0, Suse 32, Suse 64

Synopsys, Inc.

700 East Middlefield Road

Mountain View, CA 94043

www.synopsys.com

©2008 Synopsys, the Synopsys logo, Design Compiler, and PrimeTime are registered trademarks, and DC Ultra, Galaxy, Milkyway, and Star-RCXT are trademarks of Synopsys, Inc. All other products or service names mentioned herein are trademarks of their respective holders and should be treated as such. Printed in the U.S.A. 05/08.CE.08-16412.WO