DFT MAX

Adaptive Scan Compression Synthesis

Overview DFT MAX is a comprehensive scan compression synthesis and compression solution that address design and test challenges occurring in 130-nm, 90-nm and smaller process technologies. These Deep-submicron (DSM) designs are bringing new fault types which cannot be detected with tradi- tional stuck-at test techniques. These faults can only be detected with at-speed and bridging tests which result in more test vectors leading to higher costs. DFT MAX delivers push-button 10-100x test data and test time compression, thus enabling DSM testing for high fault coverage with no impact on test cost. Its unique Adaptive Scan technology generates an efficient scan architecture that delivers test compression with the smallest area. DFT MAX provides comprehensive, powerful design rule checking (DRC), including scan, boundary scan, test compression synthesis, integration and verification capabilities. It is transparently integrated within Synopsys’ Design Compiler

and the entire Galaxy™ Design Platform to achieve best timing closure and to eliminate costly iterations between design and test implementation without test expertise. It transparently supports all TetraMAX and TetraMAX DSMTest ATPG features and fault models, delivering the same very high quality test vectors and high accuracy failure diagnosis as the traditional scan methodology.

DFT MAX Features Key Benefits Adaptive Scan technology delivers 10-100x test time and test volume reduction Built-in to synthesis, it’s as easy to implement as regular scan Integration with Design Compiler Topographical Technology and IC Compiler for concurrent optimization of area, power, timing, physical and test constraints Supports low power and multi-voltage flows Complete Test DRC analysis at the Register Transfer Level (RTL) and gate level Hierarchical scan synthesis •• • • ••••••• Boundary scan synthesis and compliance checking to the 1149.1 standard Transparent integration with TetraMAX ATPG •• 10-100x test time and test volume reduction Same high test coverage and ease of use as traditional scan No impact on design timing No impact on design physical implementation Higher test quality for designs at 130-nm, 90-nm and below Tester T i me Reduct i on
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Figure 1: DFT MAX Compiler delivers 10-100X test time and test volume reduction