DFT MAX - Synopsys - #3

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•• • • Boundary Scan Synthesis And Compliance Checking To The 1149.1 Standard DFT MAX delivers a complete set of boundary scan capabilities including:TAP and BSR synthesisCompliance checking to the IEEE 1149.1 standard Boundary Scan Description Language (BSDL) file generation Functional and DC parameters vectors generation for manufacturing test Hierarchical Scan Synthesis DFT MAX To handle the test synthesis of large designs, some level of abstraction is required so that the System/Chip Integrator can reduce design time. By abstracting the DFT information in a test-model, along with timing and placement information, DFT MAX enables quick hierarchical test implementation of multi- million gate designs.
Traditional ScanAdaptive Scan Figure 4: These screen captures show how Adaptive Scan offers the same design timing, no congestion, same test coverage and 10-100x-test time reduction as traditional scan. DFT MAX enables designers to create “test-friendly” RTL. It identifies DFT rules violations early in the design cycle during the pre-synthesis stage and avoids design iterations. From RTL to gate level, the DFT rules checker validates that the design is compliant with scan rules leading to operational scan chains and the highest test coverage. The violations can be debugged through a graphical browser in Design Vision. Its compre- hensive set of rules checks for:Violations that prevent proper scan operationViolations that prevent data capture Violations that lower fault coverage The same DRC engine is run from RTL to gate level and ATPG, making it possible for designers to validate testability all the way through the design synthesis process. •• • Complete DFT Rules Checking From RTL To Gate Level 3