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In Synopsys’ unique synthesis flow (Figure 3), “Adaptive Scan” logic is synthesized at the same time as scan chain archi- tecting and stitching within the Galaxy implementation platform. Topographical scan chain ordering and partitioning provides excellent timing and area correlation with physical results using IC Compiler. This enables designers to achieve area, power, timing and DFT closure simultaneously. DFT MAX generates a SCANDEF file with detailed scan chain information which IC Compiler uses to perform further optimization to reduce area impact and decrease overall routing congestion (Figure 4). Integration With Galaxy Design Platform For Concurrent Optimization Of Area, Power, Timing, Physical And Test Constraints DFT MAX

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i ve Scan* Load10-100x Test T

Test Compression Synthesis

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DFT MAX is an extension of the existing test synthesis flow in DFT Compiler. It synthesizes scan and test compression directly from RTL to testable gates with full optimization of synthesis design rules and constraints. All test and compression require- ments specified prior to the synthesis process are met concur-rently with area, timing and power optimization. It creates a gate- level implementation with all scan design rules checked and all test and compression logic verified, leading to very high and predictable test coverage and test compression results. The implementation of DFT, including test compression, within the design synthesis environment allows problems to be found and fixed earlier in the design cycle, thus avoiding ‘schedule-killing’ design iterations. DFT MAX also has an interface to TetraMAX ATPG to transparently deliver the test architecture specification to the test pattern generation engine and seamlessly generates compressed test patterns delivering the highest test quality.

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*Patent Pend i ng Technology Figure 2: DFT MAX - Adaptive Scan technology Figure 3: Physical-aware test compression synthesis flow

Adaptive Scan Technology Delivers 10-100x Test Time And Test Volume Reduction As process technologies migrate to 130nm and below, many timing-related manufacturing defects occur, and cannot be detected with stuck-at tests alone. Additional tests that target transition delay, path delay and bridging faults are needed to improve quality. Because these tests increase the total number of patterns by 5-10x, they can lead to a substantial increase in tester time and may even exceed available ATE memory resources.DFT MAX reduces the costs of nanometer testing by providing 10-100x test data volume compression (Figure 1) within design synthesis. Using an innovative “Adaptive Scan” architecture, DFT MAX saves test time and makes it possible to include DSMTest patterns in tester configurations where memory is limited. With the industry’s most area-efficient solution, DFT MAX has virtually no impact on design timing and results in the same high test coverage using TetraMAX ATPG as traditional scan (Figure 2). 2