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| Datasheet | ||||||||||
| DFT Compiler Test Synthesis | ||||||||||
| Overview DFT Compiler - Synopsys' design-for-test (DFT) synthesis solution - delivers DFT transparently within Synopsys' logical and physical synthesis flows with fastest time to results. DFT Compiler's integration with Design Compiler® and IC Compiler® ensures DFT with seamless optimization of area, power, and timing constraints, and predictable timing closure of physically optimized scan designs. DFT Compiler enables designers to conduct in-depth testability analysis at the register transfer level (RTL) to implement the most effective test structures at the hierarchical block level, and, if necessary, to automatically repair test design rule checking (DRC) violations at the gate-level. DFT Compiler works with the DFT MAX addon to deliver high quality test compression for both stuck-at and at-speed tests, resulting in higher quality test without additional cost or design effort. | ||||||||||
| Key Features/Benefits Physical-Aware DFT Synthesis • Shortens the design cycle, eliminating design iterations and schedule risks • Increases productivity, accounting for testability early in the design • Supports low power and multi-voltage flows • Integrated with Design Compiler Topographical Technology for highest correlation of area and timing with physical results using IC Compiler • Creates STIL protocol file automatically for input to TetraMAX® ATPG RTL Test DRC • Ensures fast, accurate testability assurance at the RT level • Delivers feedback on testability violations in source-code browser • Enables RTL or gate-level test DRC and fault coverage validation • Links test DRC analysis with Design Vision graphical user interface | AutoFix • Enables automatic repair of test DRC violations at the gate-level Rapid Scan Synthesis™ Technology • Enables rapid implementation of the most effective test structures at the hierarchical block level • Hierarchical scan synthesis using test models facilitates multimillion-gate capacity Transparent Integration with TetraMAX Power-Aware ATPG • Uses the same TetraMAX® Automatic Test Pattern Generation (ATPG) engine that is used for chip-level ATPG sign-off | |||||||||