Rapid Scan Synthesis Transparent Integration With TetraMAX Power-Aware ATPG Rapid Scan Synthesis flow (Figure 5) can be used where the full optimization capabilities of DFT Synthesis is not desired to implement a quick prototype of the scan architecture. This capability enables the rapid implementation of scan chains and DFT logic to create correct-by-construction scan chains both in the logical as well as physical environments to generate a scan netlist to be handed over to ATPG for an early estimate of test coverage or test pattern count.To handle the test synthesis of large designs at the chip level, some level of abstraction may be desirable so the System/
Chip Integrator can further reduce design time. By abstracting the DFT information in a test-model, along with timing and placement information in the logical and physical synthesis domains, the designer can make fundamental DFT decisions very early on. DFT Compiler transfers all information about the scan chains to TetraMAX to automatically generate power-aware test patterns with the highest test coverage. DFT Compiler supports all existing TetraMAX ATPG algorithms and DSMTest fault models. DFT Compiler also supports proven TetraMAX ATE links for failure diagnosis and delivers a straightforward flow from tester fail to location of the defect. DFT Compiler
DFT Compiler - 33951 RTL DFT Compiler
RTL Test DRC Synthesis / QuickScan ReplacementGate-Level DRCRapid Scan Stitching
Figure 3: Automatic repair of scan rule violations Address, Data Clock QDCPQD
QDQD Embedded Memory CP Testmode Testmode QD CP CP CP
TetraMAX ATPG
Figure 4: Shadow Logic DFT for an Embedded Memory.Figure 5: Rapid Scan Synthesis Flow. AutoFix While RTL TestDRC enables designers to identify viola-
tions at the RT level, the designer has also the option to let the AutoFix capability fix these violations at the gate level during the synthesis stage, while meeting timing constraints. AutoFix focuses primarily on the controllability of clocks and asynchronous set/reset signals, since these are some of the most common testability problems. After DRC violations, the designer uses the AutoFix capability to automatically insert test logic at the gate level to fix these violations. It ensures that the netlist is testable and ready for ATPG. Since AutoFix is integrated within DFT synthesis, the testability fixes have minimal or no impact on the overall timing and area constraints of the design. Figure 3 shows an example circuit with uncon-
trollable clock and asynchronous reset inputs to a bank of flip-flops. These are gross DRC violations, which will drastically reduce the test coverage.AutoFix has also been extended to support the testing of shadow-logic around embedded
memory modules (Figure 4). Using this capability, called Shadow-LogicDFT, the designer can synthesize testability logic at the
memory module I/O to enhance the controllability and observability of the shadow-
logic around the embedded
memory module. The DFT driven placement capability in IC Compiler places the newly inserted testability logic closer to the respective ports to minimize congestion. Synopsys, Inc.700 East Middlefield Road
Mountain View, CA 94043
www.synopsys.com
©2006 Synopsys, Inc. Synopsys, the Synopsys logo and PrimeTime are registered trademarks and Physical Compiler and Design Compiler are trademarks of Synopsys, Inc. All other products or service names mentioned herein are trademarks of their respective holders and should be treated as such. Printed in the U.S.A. ©2006 Synopsys, Inc. 12/006.KF.06-15076
