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Datasheet

Design Compiler Ultra - 33951 Design Compiler Ultra Design Compiler

®

at its Best

Overview Design Compiler Ultra (DC Ultra) is the best-in-class, production RTL synthesis solution enabling users to meet today’s design challenges such as fastest timing, smallest area, lowest power consumption and highest test coverage in the shortest design cycle time. DC Ultra achieves this by concurrently applying its unique algorithms to optimize for timing, area, power and test.Innovation in synthesis has always been synonymous with Design Compiler. Continuing the trend, Synopsys now offers the latest innovation in synthesis: Design Compiler topographical technology. Topographical technology enables a predictable flow resulting in faster time to results by eliminating costly iterations between synthesis and layout. It accurately predicts post-layout results such as timing, power and area in synthesis while eliminating the need for wireload model-based approximations.

• Delivers best Quality of Results (QoR) in terms of area, timing, power and test • Correlated to physical implementation

ModuleCompiler

• Removes timing bottlenecks by creating fast critical paths
™ • Offers more flexibility for users to control optimization on specific areas of designs

DesignWare

®

DFTCompiler

• Distributed synthesis with automated chip synthesis

DesignCompilerCorrelatedQoR

® • Enables higher efficiency with integrated static timing analysis, test synthesis and power synthesis • Support for multi-voltage and multi-supplyDC Ultra is the core of Synopsys’ comprehensive RTL synthesis solution, including Power Compiler

PrimeTime

® ™ ™ , DesignWare
® , PrimeTime
® , and DFT Compiler. It is built upon the industry leading DC Expert synthesis engine, offering all the benefits of DC Expert in addition to its own unique advantages.

FormalityPowerCompiler

F i gure 1: The i ndustry’s most comprehens i ve synthes i s solut i on.