Text version of the page

Netlist Formats and Interfaces DC Ultra supports all popular industry standards formats. Circuit Netlist: Verilog, SystemVerilog, and VHDL Command Script: dcsh, TCL Interfaces: PLI, SDF, PDEF, SDC Platforms: For more M AIX (32-/64-bit) Redhat Linux (32-/64-bit) Sun Solaris (32-/64-bit) HP-UX (32-/64-bit) IB i nformat i on on Synopsys products, v i s i t us on the web at www.synopsys.com. Des i gn Comp i ler Ultra Summary DC Ultra is the synthesis solution for today’s designs offering best-in-class QoR. With its unique and comprehensive optimi- zation algorithms, correlated QoR to physical implementation with topographical technology, added user controllability, and a proven track record of countless design successes, DC Ultra continues to be the best synthesis solution for all design needs.

Existing Circuit Circuit After 7.510.29.88.2

clock period = 10

Design Compiler Ultra - 33951 logic

InputsOutputs F i gure 5: Ret i m i ng des i gns w i th reg i sters.

criticalAB AB

Existing Circuit Circuit After

logic’

critical

23 .

8.9 4.07.3

AfterBefore

9.

logic”

InputOutputs10 nsInputOutput

F i gure 4: Through log i c dupl i cat i on, DC Ultra reduces the load on the cr F i gure 6: Ret i m i ng on comb i nat i onal log i c. i t i cal path for s i gn i ficant t i m i ng i mprovements.

pipeline registers in pure combination circuits to be used to meet performance requirements as well as reduce area (Figure 6). Register retiming can be used along with datapath optimization algorithms to get the fastest pipelines. Better Control of Synthesis Cost-Function Priorities and Optimization Steps DC Ultra provides finer control over optimization to meet aggres- sive timing requirements. DC Ultra has a default cost function that prioritizes design rule requirements over timing and area constraints. By setting the appropriate priority, designers can drive synthesis to achieve the best QoR for a design. Compile directives in DC Ultra can be used to further control optimization. The compile directives allow the designer to change DC Ultra’s standard behavior. For example, a designer may have a particu- lar structure in mind and have instantiated the cells in the path. Although the overall structure should not change, it may be desir- able for Design Compiler to perform sizing and local optimization for better timing. For this set of optimizations, the global structur- ing of the logic can be disabled while enabling gate sizing. Synopsys, Inc.700 East M iddlefield Road M ountain View, CA 94043www.synopsys.com

©2007 Synopsys, Inc. Synopsys, the Synopsys logo, Design Compiler, DesignWare and PrimeTime are registered trademarks and Galaxy, M odule Compiler, and Power Compiler are trademarks of Synopsys, Inc. All other products or service names mentioned herein are trademarks of their respective holders and should be treated as such. Printed in the U.S.A. 02/07.PS.WO.07-15159