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Register Retiming Register retiming further improves QoR. It performs optimization of sequential logic by moving registers through logic boundar- ies to optimize timing with minimum area impact (Figure 5) for designs that already contain registers. The same functionality is preserved at I/O boundaries. Register retiming can also insert 2 Des i gn Comp i ler Ultra
a b c d e fa b c d e f * * MulT2 MulT2 Powerful Critical Path Synthesis DC Ultra employs various optimization algorithms throughout the synthesis process to deliver ultra-fast critical path timing. For example, immediately after the initial technology mapping, the design is not yet subjected to detailed gate-level optimization techniques. At this stage, DC Ultra performs aggressive timing driven restructuring, mapping and gate-level optimization. As a result, the subsequent detailed gate-level optimizations benefit from better overall timing-based structure. Throughout gate-level optimization, additional strategies are applied to improve the delay of the critical paths in the design. One of the techniques includes aggressive logic duplication for reducing the load seen by the critical path (Figure 4). DC Ultra looks at a larger subsec- tion of the critical path during logic duplication and can replicate many gates to reduce load of high fan-out nets, hence improving timing on critical paths through load isolation. DC Ultra will also automatically ungroup parts of the design on the critical path to achieve better area and timing. It can also buffer high fanout nets to improve total negative slack.The DC Ultra mapping algorithms also attempt to map groups of cells to wide-fan-in library cells on critical timing paths that can reduce number of logic levels and cell instances. Thus, timing, area, and power are improved.
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TopographicalTechnology• No need for wireload models• Correlates to post-layout timing, area, and power• No change to synthesis use Physical Library

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Design Compiler Ultra - 33951 z<=a*b+c*d-e-f

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Carry delayincurred once!CSAtransformation

Built for RTL desi g ners Design Compiler

+ Figure 2: The latest innovation in RTL synthesis. F i gure 3: Transformat i on of sum of products i nto a Carry Save Adder (CSA) tree. zz Topographical Technology—the Latest Innovation in Synthesis Topographical technology, the latest innovation in synthesis, delivers accurate correlation to post-layout timing, area and power without the need for wireload models. It is designed for RTL designers and requires no physical design expertise or changes to the synthesis use model (Figure 2). The accurate prediction of layout timing and area in DC Ultra is achieved through the innovative “topographical technology”. It enables RTL designers to fix real design issues while still in synthesis and generate a better start point for physical design, eliminating costly iterations. This significantly boosts RTL designers’ productivity. Topographi- cal technology shares technology with Galaxy
™ physical design, ensuring a smooth, convergent path from RTL to GDSII. Advanced Arithmetic Optimization For designs containing datapath, DC Ultra provides better QoR in terms of timing and area in less synthesis runtimes for data- path through innovative datapath optimization algorithms. With these capabilities, DC Ultra identifies arithmetic trees in your HDL and optimizes them using carry-save arithmetic techniques to minimize performance and area impact of carry propagation (Figure 3).With DC Ultra, logic synthesis users can also take advantage of superior datapath synthesis capability to generate highly opti- mized implementations of DesignWare arithmetic components. 2