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Datasheet

BSD Compiler - 33951 BSD Compiler Boundary Scan Synthesis

Overview BSD Compiler is an automated tool for the synthesis and verification of boundary scan logic in ASICs and ICs within the Design Compiler™ synthesis environment. BSD Compiler synthesizes boundary scan from the user’s RTL description utilizing DesignWare

®

JTAG components. After synthesis, a powerful and unique compliance checker in BSD Compiler verifies the boundary scan logic for compliance to the IEEE 1149.1 standard. BSD Compiler automatically creates a boundary scan description language (BSDL) file for board-level test and generates functional and DC parametric vectors for manufacturing test.

Key Benefits BSD Compiler Features Easy implementation of boundary scan in the familiar Synopsys synthesis environment Eliminates late stage iterations by early prediction of boundary scan impact on timing Quickly verifies conformance to the IEEE 1149.1 standard

RTL Design

Includes pre-verified boundary scan DesignWare components Timing and area driven boundary scan implementation using new boundary scan optimization algorithm Powerful IEEE 1149.1 compliance checking Easy-to-use interface to debug 1149.1 compliance errors Automatic BSDL file generation Automatic functional and DC parametric vector generation Verifies compliance and generates a BSDL file and manufacturing vectors on designs with existing boundary scan logic •• ••• •• • • •

BSD Compiler

ESP
® Boundary Scan Synthesis Boundary Scan Optimization 1149.1 Compliance Checking Boundary Scan Pattern Generation

DC Environment

Netlist BSDLw/BSCAN BSDL TestVectors Figure 1: Boundary Scan Flow