BSD Compiler - Synopsys - #2

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•• • Netlist, Test Vector Interface BSD Compiler supports popular industry standards for RTL input and test vector formats:RTL Input: Verilog, VHDLTest Bench: Verilog, VHDL-87 Test Vectors: WGL, STIL Verification BSD Compiler automatically generates a BSDL file, the standard description language for devices complying with the IEEE 1149.1 standard. BSD Compiler generates both functional and DC parametric vectors for manufacturing test. BSD Compiler can also generate a BSDL file and test vectors for designs with existing boundary scan logic. For information related to products, training or support services, please visit the Web at www.synopsys.com. For sales assistance, call 1 650 584 5000. BSD Compiler Powerful IEEE 1149.1 Compliance Checking One of the unique features of BSD Compiler is its ability to perform 1149.1 compliance checking utilizing symbolic simulation techniques. This eliminates the need for extensive gate-level simulation to verify conformance to the IEEE 1149.1 standard. BSD Compiler provides an easy-to-use interface to debug problems due to 1149.1 compliance errors. The compliance checking capability also supports designs with existing boundary scan logic.BSD Compiler provides a highly integrated flow for boundary scan synthesis, verification and pattern ge neration in the Design Compiler environment.
Figure 2: BSD Compiler provides a highly integrated flow for boundary scan synthesis, verification and pattern generation in the Design Compiler environment Boundary Scan Synthesis and Optimization BSD Compiler is tightly integrated in the Design Compiler synthesis flow, which ensures optimized implementation of design with boundary scan logic. After reading the RTL description, BSD Compiler synthesizes boundary scan logic- based on the user’s JTAG specification. Once the design is mapped to a technology library, BSD Compiler optimizes the boundary scan architecture by intelligently selecting boundary scan cells to meet top-level area and timing constraints.BSD Compiler synthesizes boundary scan logic using Synopsys DesignWare JTAG components which are included with the tool. Since the tool uses optimized DesignWare boundary scan components, the need to manually design the boundary scan cells is eliminated. The DesignWare test access port (TAP) is configurable to accommodate individual designs, and with a few simple commands in BSD Compiler, IEEE 1149.1 compliance is assured early in the design cycle. Synopsys, Inc.700 East Middlefield Road Mountain View, CA 94043 www.synopsys.com
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