Synthesized Clock Generator - Stanford Research Systems - #1

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· Clocks from DC to 2.05GHz · Random jitter <1ps rms · 16 digits of frequency resolution · 80ps rise and fall times · CMOS, PECL, ECL, LVDS, RS-485 outputs · Phase control and time modulation · PRBS for eye-pattern testing (opt.) · OCXO and rubidium timebase (opt.) · CG635 ... $2995 (U.S. list) The CG635 generates extremely stable square wave clocks between 1 ìHz and 2.05 GHz. The instrument's high frequency resolution, low jitter, fast transition times, and flexible output levels make it ideal for use in the development and testing of virtually any digital component, system or network. Clean clocks are critical in systems that use high-speed ADCs or DACs. Spurious clock modulation and jitter create artifacts and noise in acquired signals and in reconstructed waveforms. Clean clocks are also important in communications systems and networks. Jitter, wander, or frequency offsets can lead to high bit error rates, or to a total loss of synchronization. The CG635 can provide the clean, stable clocks required for the most critical applications. Output Drivers The CG635 has several clock outputs. The front-panel Q and Q outputs provide complementary square waves at standard logic levels (ECL, PECL, LVDS or +7 dBm). The square wave amplitude may also be set from 0.2V to 1.0V, with an offset between -2 V and +5 V. These outputs operate from DC to 2.05 GHz, have transition times of 80 ps, a source impedance of 50 Ù, and are intended to drive 50 Ù loads. Output levels double when these outputs are unterminated. The front-panel CMOS output provides square waves at standard logic levels. The output may also be set to any CG635 Synthesized Clock Generator Synthesized Clock Generator CG635 . DC to 2.05 GHz low-jitter clock generator www.thinkSRS.com Stanford Research Systems phone: (408)744-9040 www.thinkSRS.com