Low-Voltage/Low-Power Solutions - Silicon Laboratories - #1

• Single cell/dual-cell operation

- One-cell mode supports 0.9 to 1.8 V operation

- Dual-cell mode supports 1.8 to 3.6 V operation

• Integrated high-efficiency dc-dc boost converter

• Integrated low drop out (LDO) voltage regulator

• Multiple internal oscillators

- smaRTClock oscillator

- Low power 20 MHz oscillator

- Precision 24.5 MHz oscillator with spread spectrum mode

• Ultra-low current sleep mode and fast wake

• 25 MHz, single-cycle 8051 compatible CPU with low active-mode current

• Unprecedented functional density

- 64 kB Flash memory

- 4 kB of RAM

- 4 x 4 mm package

• Burst mode 10-bit ADC with internal fast start-up VREF

• Capacitive touch sense support

- Two on-chip voltage comparators

- Up to 23 capacitive touch sense inputs

• Portable personal medical products

• Remote controls

• Portable audio

• Consumer electronics

• Wireless sensors and security

• Wireless meter reading

• Industrial monitoring and control

COMPETITION ECLIPSE

WWW.SILABS.COM/P0INT9

The C8051F9xx product family is the industry's first MCU family capable of operating down to 0.9 V and up to 3.6 V, enabling single-cell battery operation as well as dramatically increasing battery life for dual-cell applications. With an integrated dc-dc converter, the C8051F9xx has been designed to provide a fast wake-up time, low active-mode, and ultra-low sleep mode current consumptions. The C8051F9xx family not only provides high performance while saving power but also unprecedented functional density in a small footprint. The C8051F9xx is the first line of MCUs to integrate 64 kB of Flash and 4 kB of RAM into a 4 x 4 mm package while also integrating a 10-bit, 300-ksps analog-to-digital converter (ADC) with an internal fast wake-up voltage reference, a smaRTClock timing module, and multiple internal oscillator options to provide a true system-on-chip solution.

C8051F9xx

Port I/O Configuration

CIP-51 8051 Controller Core

Power On Reset/PMU

Digital Peripherals

64k Byte ISP Flash Program Memory

UART

Port 0

Drivers

Reset

Timers 0, 1, 2, 3

256 Byte SRAM

Debug/ Programming Hardware

C2CK/RST

Priority Crossbar

Decoder

4096 Byte XRAM

PCA/

WDT

C2D

CRC Engine

SMBus

VDD/DC+-4— GND/DC- ■*-

♦ VREG

Digital Power

Analog

Power

SYSCLK

Crossbar Control

Precision 24.5 MHz Oscillator

Analog Peripherals

DC/DC Converter

VBAT"

Low Power 20 MHz Oscillator

6-bit

IREF

GND-

External

Oscillator

Circuit

XTAL 1

XTAL 2

Port 2 Drivers

Internal

dto< External T~ VREF I—

VDD VREF I Temp IsensQr

XTAL 3

10-bit

32 kHz

Oscillator

py u *

300

XTAL 4-«

ADC

GND

smaRTClock Alarm „

smaRTClock State Machine

Comparators

System Clock Configuration