SHTxx Application Note PROFESSIONAL ESD, Latch-Up and EMC ESD stress test was performed using a TMT Verifier II s/n 1042049 equipment according to table below: Stress Level Stressed Pin Reference Polarity 2 kV SCK DATA 3 positive pulses then 3 negative pulses SCK GND DATA GND SCK VDD DATA VDD GND VDD
Table 1 summarizes the tested configurations of the SHxx device The SHTxx passes the described Human-Body Model Test. Further details about the ESD test of SHTxx can be found in [Pluto1] (Report available on request at SENSIRION). No further test with higher voltages and other models (such as Machine Model, Charged Device Model, or Charged-Cable Model) have been performed to date. If more stringent specifications are required please contact SENSIRION for the latest status on the SHTxx ESD qualification. Passing the Human-Body Model test according to the described standards means that the SHTxx is well protected against ESD if normal precautions are taken when handling the device. In case extreme discharge protection is required an additional protection circuit according to Figure 3 can be implemented. VDDin VDDGND p ut from SHTxx GND output to SHTxx
Figure 3 Additional external Protection circuits for SHTxx device (only necessary when the device has to be protected against extreme electrostatic energy, above 100 Ws)

3 Latchup

Isolation of the individual diodes, transistors and capacitors from each other in an integrated cuircuit, such as the SHTxx, is achieved by reverse-biased PN junctions. These junctions form NPN and PNP structures with adjacient junctions which result in parasitic thyristors. These parasitic thyristors may be undesirably triggered in various ways [TI2000]. 1. If there is a voltage at the input or output of the SHTxx which is more positive than the supply or more negative than the ground connection current flows into the gate of the parasitic thyristor. If the amplitude and duration of the current are sufficient the thyristor is triggered. With lines of several meters in length and overshoots the probability that the thyristor might be triggered must be taken into account. 2. An electrostatic discharge can trigger the parasitic thyristor. Even if the electrostatic discharges have a duration of only a few tens of nanoseconds the complete chip may be flooded with charge carries, which then flow away slowly, resulting in the triggering of the thyristor. 3. The parasitic thyristor may be triggered by a high supply voltage - far higher than the value given in data sheet. Although these conditions violate the specifications given in the SHTxx data sheet they may occur during uncontrolled events during operation. The SHTxx device was designed obeying state-of-the art precautions to reduce the thyristors sensitivity to the maximum thus to avoid latch-up in all above mentioned situations. In order to verify the latch-up immunity the SHTxx device are tested according to JEDEC Std 78. Figure 4 shows the test setup. The test was performed at 85°C using a ORYX 11000EX professional test system.
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