Catalogue E497 PC/104 48 LINES TTL DIGITAL I / O
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I/O Map

The E497-x I/O base address can be settled via the JP1 configuration. Each one of the six parts ofthe JP1 multiple jumper is used by the glued logic to perform the I/O range decoding. More exactly,each single jumper is used to perform the address comparison as shown by the following table: JP1Address in comparison 1-2SA4 3-4SA5 5-6SA6 7-8SA7 9-10SA8 11-12SA9 In example, to map the board at 0x330 I/O address, the following JP1 configuration is achieved: SA0=x β‡’ SA1=x β‡’ SA2=x β‡’ SA3=0
(**) β‡’ 0x330SA9=1 SA4=1 β‡’ JP1[1-2]Opened
(*) SA5=1 β‡’ JP1[3-4]Opened
(*) SA6=0 β‡’ JP1[5-6]Closed
(*) SA7=0 β‡’ JP1[7-8]Closed
(*) SA8=1 β‡’ JP1[9-10]Opened
(*) β‡’ JP1[11-12]Opened
(*) (*) a closed jumper means a logic “0” and a opened one means a logic “1”(**) for all E497 I/O address, SA3 must be always 0. This means that the board occupies 8-byte of I/O space but all possible base addresses must bespaced by 16-byte (i.e. 0x280, 0x290, 0x2A0…). 4
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