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| | | MEMORY AND STORAG | | |
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| | | ASYNCHRONOUS SRAM ORDERING INFORMATION | | |
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| | | . M | | K | | . G | | .S | | (tAA) | | |
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| | | A: 2nd Generation B: 3rd Generation C: 4th Generation D: 5th Generation E 6th Generation F: 7th Generation G: 8th Generation H: 9th Generation | | - CMOS C LPSRAM P L LPSRAM TFT C LPSRAM 10:100ns 12:120ns 15:150ns 25: 25ns(only fCMOS Cell) 30:300ns 35: 35ns(except Poly Load cell) 45: 45ns(except fCMOS Cell) 55: 55ns 60: 60ns(only fCMOS Cell) 70:70ns 85:85ns 90: 90ns(only fCMOS Cell) DS Daisychain Sample | | C | | |
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| | | .A SRAM: | | |
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| | | . S | | C | | |
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| | | E: Corner Vcc/Vss + Fast SPAM F:fCMOS Cell + LPSPAM H: High Speed(LPSPAM) X: High Voltage(LPSPAM) J: BICMOS L: Poly Load Cell + LPSPAM P Center Vcc/Vss + Fast SPAM T:TFT Cell + LPSPAM . D | | |
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| | | A: TBGA(LF) C: CHIP BIZ E: TBGA G: SOP J:SOJ L:TSOP1-0813.4F(LF) P:TSOP1-0820F(LF) | | B: SOP(LF) D: DIP F: FBGA H: BGA K: SOJ(LF) | | |
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| | | 06:64K 10: 1M | | 08: 256K 16: 16M | | 09: 512K 20: 2M | | |
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| | | ■ H S | | LPSRAM | | |
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| | | | | | | | | | | | | | | | 30: 3M | 32: 32M | 40: 4M | Q: TSOP2-400R(LF) | R: TSOP-R | 20: 20ns | | 25: 25ns | | | | 60: 6M | 64: 64M | 80: 8M | T: TSOP | U: TSOP2-400(LF) | - H V | LPSRAM | | | | | | | | W: WAFER | Z: UBGA | 55: 55ns | 70: 70ns | 85: 85ns | | | | . O | | | | | - C V /V | F SRAM | | | | | 01 : x1 | 04: x4 | 08: x8 | * Exception | | 10: 10ns | 12: 12ns | 13: 13ns | | | | 16: x16 | 18: x18 | 24: x24 | - MFSRAM B- | | 15: 15ns | 17: 17ns | 20: 20ns | | | | 32: x32 | | | 32-SOJ-300 > S | | 25: 25ns | 30: 30ns | 35: 35ns | | | | | | | 28-SOJ-300 > S | | 45 :45ns | | | | | | .V | | | - K/ M/ M/ M LPSRAM | - BICM OS C | V /V F | SRAM | | | | 5: 1.5V | | C: 5.0V | 32-TSOP1-0813.4F > Y | | 06: 6ns | 08: 8ns | 09: 9ns | | | | Q: VDD 3.0V/VDDQ 1.8V | | 32-TSOP1-0813.4 > Y | | 10: 10ns | 12: 12ns | 13: 13ns | | | | R 1.65V~2.2V | | | 32-TSOP1-0813.4R > N | | 15: 15ns | 17: 17ns | 20: 20ns | | | | S: 2.5V | T2.7V~3.6V | U:3.0V | - M LPSRAM | | 25: 25ns | | | | | | V: 3.3V | W:2.2V~3.3V | | 32-TSOP2-400F > V | | 30: 30ns(only Center Vcc/Vss + Fast SRAM) | | | | | | | | | | | | | | | |
| | | 35: 35ns(only Center Vcc/Vss + Fast SRAM) 7A: 7.2ns(only BICMOS) 8A: 8.6ns(only BICMOS) DS Daisychain Sample - A SRAM COMMON 00: NONE (Containing Wafer, CHIP BIZ, Exception code) | | |
| | | 32-TSOP2-400R > M | | |
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| | | .M | | |
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| | | C S | | |
| | | 1: CS Low Active 2:CS1,CS2 - Dual Chip Select Sgnal 3: Sngle Chip Select with /LB,/UB(tOE) 4: Sngle Chip Select with /LB,/UB(tCS) 5: Dual Chip Select with /LB,/UB(tOE) 6: Dual Chip Select with /LB,/UB(tCS) 7:1/Os Control with /BYTE 8: CDMA Function 9: Multiplexed Address A: Mirror Chip Option | | |
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| | | - COMMON T P A: Automotive,Normal B: Commercial,Low Low C: Commercial,Normal D: Extended,Low Low E Extended,Normal F: Industrial,Low Low I: Industrial,Normal L: Commercial,Low M: Military,Normal N: Extended,Low P: Industrial,Low Q: Automotive,Low R Industrial,Super Low T Extended,Super Low U: Commercial,Ultra Super Low 0: NONENONE - AFER CHIP BI L D 0: NONE,NONE 1 : Hot DC sort 2: Hot DC,selected AC sort 3: Cold/Hot Deselected AC sort | | |
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| | | .P | | T | | |
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| | | - Common to all products, except of Mask ROM - Divided into TAPE & REEL(In Mask ROM, divided into TRAY, AMMO Packing Separately) | | |
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| | | T | | P | | T | | N M | | |
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| | | | | | | | | | | C | TAPE & REEl | T | | | | | Other (Tray, Tube, Jar) | 0 (Number) | | | | | Stack | S | | | | C | TRAY | Y | | | | M | ROM AMMO PACKING | A | | | | M | MODULE TAPE & REEl | P | | | | | MODULE Other Packing | M | | | | | | | | | | |
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| | | 16a | | |
| | | BR-06-ALL-001 | | SEPTEM BER 2006 | | |
| | | SAMSUNG SEMICONDUCTOR, INC. | | |
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