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Vectis range of pipelined FFT cores
(v1.02) May 14, 2004
‘HiSpeed’ Product Specification
OVERVIEW
This document describes the RFEL Vectis ‘HiSpeed’ range of Pipelined FFT (PFFT) cores. The cores process complex input data in continuous real time, with no gaps in the data, at complex data rates in excess of 100 MS/s. This document provides details of the cores and design services available from RFEL. Vectis HiSpeed cores are intended for use in applications where processing speed is critical and optimum use of available silicon is required. The cores are available for licence in netlist form as a component ready to be combined with customer’s own IP. Alternatively, where the core is to be the only contents of an FPGA, it can be provided as a programming bitstream; in this case RFEL would provide a separate design services contract.
FEATURES
? Continuous real time processing of complex data in excess of 100MS/s ? Compatible with 200MS/s ADC using RFEL’s optional DHBF core ? Fully pipelined design ? Targeted at Xilinx and Altera FPGA families ? 8 to 128K-point versions available (longer lengths by request) ? Bit-width and bit-growth adjustable at factory ? Twiddle bit-width adjustable at factory ? Internal memory partitioning adjustable at factory ? Can be used for real-input FFTs with additional modules ? Fully bit-true parameterisable models are available ? Optional input buffer and bit reverser ? FFT and IFFT functionality ? 2xOversampled option.
APPLICATIONS
? Wide-band
filter banks ? Communications systems ? Electronic warfare (radar, sonar, surveillance) ? Medical instrumentation ? Test instrumentation ? Real-time spectral analysis ? Multi-channel systems, where many low speed channels are interleaved through the high-speed core. © rf engines limited all rights reserved http://www.rfel.com Tel: +44(0)1983 550330
