Serial F-RAM Memory FM24C512 - Ramtron - #5

operation for both writes and reads is explained below.

All writes begin with a Slave Address, then a memory address. The bus master indicates a write operation by setting the LSB of the Slave Address to a '0'. After addressing, the bus master sends each byte of data to the memory and the memory generates an Acknowledge condition. Sequential bytes may be written through the address space however care must be taken when auto-incrementing. The memory is separated into an upper and lower address space. The auto-increment feature of the device will cause the address to wrap from 7FFFh to 0000h in the lower half and wrap from FFFFh to 8000h for the upper half of the memory.

Unlike other nonvolatile memory technologies, there is essentially no write delay with FRAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay on the bus. The entire memory cycle occurs in less time than a single bus clock. Therefore, any operation including a read or write can occur immediately following a write. Acknowledge polling, a technique used with EEPROMs to determine if a write has completed is unnecessary and will always return a ready condition.

Internally, an actual memory write occurs after the 8^th data bit is transferred. It will be complete before the Acknowledge is sent. Therefore, if the user desires to abort a write without altering the memory contents, this should be done using a Start or Stop condition prior to the 8^th data bit. The FM24C512 uses no page buffering.

The memory array can be write protected using the WP pin. Pulling the WP pin high will write-protect all addresses. The FM24C512 will not acknowledge data bytes that are written when WP is active. In addition, the address counter will not increment if writes are attempted to these addresses. Setting WP low will deactivate this feature. WP is internally pulled down. The state of WP should remain stable from the Start command until the address is complete.

Figure 5 and 6 below illustrate both a single-byte and multiple-write.

After the FM24C512 (as receiver) acknowledges the Slave Address, the master can drive the remaining portion of the memory address for a write operation. The complete address is specified by the A15 bit in the Slave Address and two additional bytes (A14-A0). The first address byte specifies A14 — A8, where the first of the eight bits is a "don'tcare". Following the upper address byte is the lower byte (A7 - A0). The address value A(14:0) is latched internally. The MSB A15 is not latched. Each access causes the latched address value to be incremented automatically. The current address is the value that is held in the latch, either a newly written value or the address following the last access. The current address will be held as long as power remains or until a new value is written. Reads always use the current address, however A15 must be specified. A random read address can be loaded by starting a write operation as explained below.

After transmission of each data byte, just prior to the acknowledge, the FM24C512 increments the internal address latch. This allows the next sequential byte to be accessed with no additional addressing externally. When auto-incrementing, the user must be aware that the address DOES NOT increment from 7FFFh to 8000h and DOES NOT wrap from FFFFh to 0000h. The memory should be treated as two separate address spaces, an upper and lower. When the last address in the lower half (7FFFh) is reached, the address rolls over to 0000h. Likewise when the last address in the upper half (FFFFh) is reached, the address rolls over to 8000h.

After the address information has been transmitted, data transfer between the bus master and the FM24C512 can begin. For a read operation the FM24C512 will place 8 data bits on the bus then wait for an Acknowledge from the master. If the Acknowledge occurs, the FM24C512 will transfer the next sequential byte. If the Acknowledge is not sent, the FM24C512 will end the read operation. For a write operation, the FM24C512 will accept 8 data bits from the master then send an acknowledge. All data transfer occurs MSB (most significant bit) first.

The FM24C512 is designed to operate in a manner very similar to other 2-wire interface memory products. The major differences result from the higher performance write capability of FRAM technology. These improvements result in some differences between the FM24C512 and a similar configuration EEPROM during writes. The complete

Rev. 1.0 Aug. 2006

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