Serial F-RAM Memory FM24C512 - Ramtron - #2

A1, A2

Input

Address 1, 2: These pins are used to select one of up to 4 devices of the same type on the same two-wire bus. To select the device, the address value on the two pins must match the corresponding bits contained in the device address. The address pins are pulled down internally.

WP

Input

Write Protect: When WP is high, the entire array will be write-protected. When WP is low, all addresses may be written. This pin is internally pulled down.

SDA

I/O

Serial Data/Address: This is a bi-directional input used to shift serial data and addresses for the two-wire interface. It employs an open-drain output and is intended to be wire-ORd with other devices on the two-wire bus. The input buffer incorporates a Schmitt trigger for improved noise immunity and the output driver has slope control for falling edges. An external pull-up resistor is required.

SCL

Input

Serial Clock: The serial clock input for the two-wire interface. Data is clocked out of the device on the SCL falling edge, and clocked in on the SCL rising edge. The SCL input also incorporates a Schmitt trigger input for improved noise immunity.

VDD

Supply

Supply Voltage: 5 V

VSS

Supply

Ground