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Eclipse II Family Data Sheet

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Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM

Device Highlights

Advanced Clock Network

• Multiple dedicated low skew clock networks• High drive input-only networks• Quadrant-based segmentable clock networks• User programmable Phase Locked Loops (PLL)

Flexible Programmable Logic

• As low as 14 µA standby current• 0.18 µm, six layer metal CMOS process• 1.8 V VCC, 1.8/2.5/3.3 V drive capableI/O• Up to 4,002 dedicated flip-flops • Up to 55.3 K embedded SRAM bits • Up to 310 I/O• Up to 335 user available pins• Up to 320 K system gates • IEEE 1149.1 boundary scan testing compliant

Embedded Computational Units (ECUs)

Hardwired DSP building blocks with integrated Multiply, Add, and Accumulate functions.

Security Features

technology that protects intellectual property from design theft and reverse engineering. No external configuration memory needed; instant-on at power-up. The QuickLogic products come with secure ViaLink

Embedded Dual Port SRAM

• Up to twenty-four 2,304 bit dual port high performance SRAM blocks • RAM/ROM/FIFO wizard for automatic configuration• Configurable and cascadable aspect ratio Figure 1: Eclipse IIBlock Diagram
PLL EmbeddedRAMBlocks PLL EmbededComputationalUnits

Programmable I/O

• High performance I/O cell • Programmable slew rate control • Programmable I/O standards:
Fabric LVTTL, LVCMOS, LVCMOS18, PCI, GTL+, SSTL2, and SSTL3
PLL EmbeddedRAMBlocks PLL Independent I/O banks capable of supporting multiple standards in one device I/O register configurations: Input, Output, Output Enable (OE)
•• • •• • © 2007 QuickLogic Corporation www.quicklogic.com 1