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PolarPro

®

Solution Platform Family Data Sheet

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Family of Solution Platforms Integrating Low Power Programmable Fabric and Embedded SRAM

Platform Highlights

Very Low Power (VLP) Mode

•The QuickLogic PolarPro Solution Platform family has a special VLP pin whichcan enable a low power sleep mode that significantly reduces the overall power consumption of the platform by placing the platform in standby. •Enter/exit VLP mode from/to normal operation in less than 250 µs (typical).

Flexible Programmable Fabric

•8 to 240 customizable building blocks (CBBs) (see Programmable Fabric Architectural Overview on page 5 for a detailed explanation of CBBs)•As low as 2.2 µA standby current •1.8 V core voltage, 1.8/2.5/3.3 V drive capableI/Os•9 Kbits to 220 Kbits of SRAM •Embedded synchronous/asynchronous FIFO controllers•Up to two user configurable clock managers (CCMs) (see

JTAG

Configurable Clock Manager on page 6 for an explanation of CCM)•48 to 244 programmable I/Os available•Ideal platform to implement additional proven system blocks (PSBs), custom functions, glue logic and processor interface QuickLogic PolarPro Solution Platform family supports IEEE 1149.1 boundary scan or post- manufacturing testability. External access to this feature can be completely disabled.

Solution Highlights

•Integrated, single-chip solution for multiple peripheral host controllers and interfaces to reduce both system BOM cost and board space.•Programmable fabric for proven system blocks and custom functions.•Fast time-to-market with QuickLogic’s complete low power connectivity solutions.

Programmable I/O

•Bank programmable drive strength•Bank programmable slew rate control•Independent I/O banks capable of supporting multiple I/O standards in one platform•Native support for DDRIOs in some packages •Bank programmable I/O standards: LVTTL, LVCMOS, LVCMOS18, PCI, SSTL2, SSTL3 and SSDL18•Can be used for level shifter and I/O voltage translator
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