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QuickLogic PolarPro

®

Device Data Sheet — 86-Pin TFBGA QL1P100

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Combining Low Power, Performance, Density, and Embedded RAM

Device Highlights

16 quad clock networks per device

Low Power Programmable Logic

4 quad clock networks per quadrant•One user Configurable Clock Manager (CCM) •As low as 2.2 µA •0.18 µm, six layer metal CMOS process•1.8 V core voltage, 1.8/2.5/3.3 V drive capableI/Os•36 kilobits of SRAM •48 I/Os available•100,000 system gates•Nonvolatile, instant-on •IEEE 1149.1 boundary scan testing compliant

Very Low Power (VLP) Mode

•QuickLogic PolarPro has a special VLP pin whichcan enable a low power sleep mode that significantly reduces the overall power consumption of the device by placing the device in standby•Enter VLP mode from normal operation in less than 250 µs (typical)•Exit from VLP mode to normal operation in less than 250 µs (typical)

Embedded Dual-Port SRAM

•Eight dual-port 4-kilobit high performance SRAM blocks •True dual-port capability•Embedded synchronous/asynchronous FIFO controller•Configurable and cascadable aspect ratio

Security Links

There are several security links to disable JTAG access to the device. Programming these optional links completely disables access to the device from the outside world and provides an extra level of design security not possible in SRAM-based FPGAs.
Figure 1: QuickLogic PolarPro Block Diagram

Programmable I/O

DDR/GPIO CCM •Bank programmable drive strength •Bank programmable slew rate control•Independent I/O banks capable of supporting multiple I/O standards in one device•Bank programmable I/O standards: LVTTL, LVCMOS, LVCMOS18, PCI, SSTL2, SSTL3 and SSDL18
Embedded RAM BlocksFIFO Controller GPIOGPIOGPIO Fabric

Advanced Clock Network

FIFO Controller GPIOGPIOGPIOGPIO GPIO •Multiple low skew clock networks
Embedded RAM Blocks GPIOGPIOGPIOGPIO DDR/GPIODDR/GPIODDR/GPIO 1 dedicated global clock network 4 programmable global clock networks •Quadrant-based segmentable clock networks
•• • • • • © 2008 QuickLogic Corporation www.quicklogic.com 1