| Military FPGA ■ Mil Std 883 and Mil Temp Ceramic ■ Mil Temp Plastic Guaranteed -55 to +125oC High Performance and High Density ■ Densities up to 90,000 usable PLD gates with 316 I/Os ■ Multiple dual-port RAM modules, organized in user-configurable 1,152-bit blocks Security: The ViaLink technology is inherently secure and virtually impossible to reverse engineer. The interconnect is more secure than an ASIC and can be programmed in a secure location. JTAG: Full JTAG IEEE 1149.1 compliant Mixed Voltage Systems: pASIC 3 and QuickRAM families drive standard TTL levels. The I/Os are compatible with 5.0 and 3.3 V devices. Speed: Able to perform in systems operating at greater than 200 MHz over the entire military temperature range. Low Power Consumption: 90mA at 50 MHz, 300 mA at 200 MHz Routability: 100% guaranteed routability with 100% utilization and 100% pin-out stability through design revisions and retro-fitting. |