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EclipsePlus Family Data Sheet • • • • • •

Combining Performance, Density, and Embedded RAM

Device Highlights

Advanced Clock Network

•Nine global clock networks:

Flexible Programmable Logic

One dedicated •0.25 µm five layer metal CMOS process•2.5 V V Eight programmable•20 quad-net networks—five per quadrant •16 I/O controls—two per I/O bank •Four phase locked loops
CC , 2.5/3.3 V drive capable I/O•Up to 4,032 logic cells•Up to 583,008 system gates •Up to 347 I/O pins

Embedded Computational Units Embedded Dual-Port SRAM

ECUs provide integrated multiply, add, and accumulate functions.

•Up to thirty-six 2,304-bit dual-port high performance SRAM blocks •Up to 82,900 RAM bits•RAM/ROM/FIFO wizard for automatic configuration•Configurable and cascadable
Figure 1: EclipsePlus Block Diagram Memory - Dual Port RAM Memory - Dual Port RAMPLL PLL PLL PLLEmbedded Computational Units

Programmable I/O

High Speed Logic Cells583K Gates

•High performance enhanced I/O (EIO)—less than 3 ns Tco•Programmable slew rate control •Programmable I/O standards: LVTTL, LVCMOS, PCI, GTL+, SSTL2,and SSTL3 Eight independent I/O banks Three register configurations: input, output, and output enable
•• • •• • © 2006 QuickLogic Corporation www.quicklogic.com 1