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NXP Semiconductors
UDA1342TS Audio CODEC

UDA1342TS Audio CODEC

Product catalog summary

Features
The UDA1342TS is a 24-bit audio CODEC supporting sample frequencies from 16 to 110 kHz. It includes separate power control for ADC and DAC, digital silence detection, and supports multiple data interface formats such as I2S-bus, MSB-justified, and LSB-justified. It offers digital sound processing features like volume and tone control, and operates in slave mode only.

Applications
This CODEC is ideal for MiniDisc home and portable applications, especially in low-voltage, low-power digital audio equipment with recording and playback capabilities.

General Description
The UDA1342TS integrates a 4-channel ADC and a 2-channel DAC with signal processing features using bitstream conversion techniques. It supports various data formats and offers sound processing features controllable via L3-bus or I2C-bus interfaces.

Quick Reference Data
The device operates with supply voltages between 2.7V and 3.6V, with specific current requirements for ADC and DAC operations. It supports ambient temperatures from -40°C to +85°C.

Functional Description
The system clock operates in slave mode with selectable frequencies. The ADC front-end includes programmable gain stages, and the device supports double differential mode for enhanced sound quality. The digital mixer allows mixing of ADC output and digital input signals, with measures to prevent clipping.

Pinning
The UDA1342TS features 28 pins, including analog and digital supply pads, input and output pads, and control interfaces for system clock, L3-bus, and I2C-bus.

Block Diagram
The block diagram illustrates the integration of ADC, DAC, digital interfaces, and DSP features within the UDA1342TS.

Additional Features
The device includes a noise shaper operating at 64fs and a Filter Stream DAC for converting 1-bit data streams into analog signals.

Digital-to-Analog Conversion
The UDA1342TS uses a noise shaper to convert digital signals to analog output voltage, achieving high signal-to-noise performance and low clock jitter sensitivity.

Digital Interface
The UDA1342TS supports various data input/output formats, including I2S-bus, MSB-justified, and LSB-justified formats with data word lengths up to 24 bits.

Sampling Speed
The device operates with sample frequencies from 16 to 110 kHz and can accept double and quad data speeds with limitations on feature usage.

Power-on Reset
An internal power-on reset circuit resets the test control block, setting digital sound processing features to default.

Control Modes
The UDA1342TS can be controlled via static pin, I2C-bus, or L3-bus modes, each with specific pin functions and controllable features.

L3-bus Interface
This interface allows control of digital processing and system features via a microcontroller.

I2C-bus Interface
Similar to the L3-bus mode, the I2C-bus mode allows control of all features using the same register addresses.

Communication Protocols
The UDA1342TS uses the I2C-bus for communication, with detailed write and read cycle processes.

Register Mapping
The document provides a detailed map of control registers with default values at power-on reset.

Operational Modes and Settings
Various settings are available for the ADC and DAC, including reset, quick mode switch, and more.

Volume and Gain Control
The document outlines the DAC volume control, DAC mixer volume control, and ADC mixer gain control.

Limiting Values and Handling
The document specifies the absolute maximum ratings, handling precautions for electrostatic discharge, and quality specifications.

Liability and Warranty
NXP Semiconductors limits its liability for damages related to its products and disclaims suitability for life-critical systems.

Product Use and Applications
NXP products are not warranted for life support or safety-critical systems. Customers are responsible for testing and ensuring product suitability for their applications.

Specifications and Ratings
Exceeding specified limiting values can cause permanent damage to devices.

Export Control and Automotive Use
The document and products may be subject to export control regulations. Non-automotive qualified products are not suitable for automotive use.

Trademarks and Contact Information
The I2C-bus logo is a trademark of NXP B.V. For more information, visit NXP's website or contact sales via email.

Catalog excerpts

INTEGRATED CIRCUITS DATA SHEET UDA1342TS Audio CODEC Product specification Supersedes data of 2000 Mar 29 2000 Jul 31

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NXP Semiconductors Product specification Audio CODEC UDA1342TS CONTENTS 1 3 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 8.2 8.2.1 8.2.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.14.1 8.14.2 8.14.3 8.15 8.15.1 8.15.2 8.15.3 8.15.4 8.15.5 8.16 8.16.1 8.16.2 8.16.3 8.16.4 8.16.5 System clock ADC analog front-end Application with 2 V (RMS) input Double differential mode Decimation filter (ADC) Digital mixer (ADC) Interpolation filter (DAC) Mute Digital mixer (DAC) Noise shaper Filter stream DAC Digital interface Sampling speed Power-on reset Control modes Static pin mode System clock setting...

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NXP Semiconductors Product specification Audio CODEC 1 UDA1342TS FEATURES General • 2.7 to 3.6 V power supply • 5 V tolerant digital inputs • High pin compatibility with UDA1341TS • 24 bits data path • Selectable control via L3-bus interface, I2C-bus interface or static pin control; choice of 2 device addresses in L3-bus and I2C-bus mode Advanced audio configuration • Separate power control for ADC and DAC • 4 channel (2 × stereo) single-ended inputs with programmable gain amplifiers and 2 channel (1 × stereo) single-ended outputs configuration • ADC and Programmable Gain Amplifiers (PGA) plus...

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NXP Semiconductors Product specification Audio CODEC 4 UDA1342TS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA(ADC) ADC analog supply voltage 2.7 3.0 3.6 V VDDA(DAC) DAC analog supply voltage 2.7 3.0 3.6 V VDDD digital supply voltage 2.7 3.0 3.6 V IDDA(ADC) ADC analog supply current 1 ADC + 1 PGA enabled − 10.0 − mA 2 ADCs + 2 PGAs enabled − 20.0 − mA all ADCs + all PGAs power-down − 200 − μA operating − 6.0 − mA DAC power-down − 250 − μA operating − 9.0 − mA ADC power-down − 4.5 − mA DAC power-down − 5.5 − mA −40 − +85 °C − 0.9 − V at −1 dB − −90 − dB at...

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NXP Semiconductors Product specification Audio CODEC SYMBOL UDA1342TS PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Digital-to-analog convertor Vo(rms) output voltage (RMS value) at 0 dB (FS) digital input; note 1 − 0.9 − V (THD+N)/S48 total harmonic distortion-plus-noise to signal ratio at fs = 48 kHz at 0 dB − −90 − dB at −60 dB; A-weighted − −40 − dB total harmonic distortion-plus-noise to signal ratio at fs = 96 kHz at 0 dB − −83 − dB at −60 dB; A-weighted − −39 − dB S/N48 signal-to-noise ratio at fs = 48 kHz code = 0; A-weighted − 100 − dB S/N96 signal-to-noise ratio at fs = 96 kHz code = 0;...

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NXP Semiconductors Product specification Audio CODEC 6 UDA1342TS BLOCK DIAGRAM VDDA(ADC) handbook, full pagewidth VSSA(ADC) 3 VINL2 VDDD 1 10 VADCN 7 11 5 6 8 ADC ADC 2 4 PGA PGA ADC UDA1342TS 9 ADC DECIMATION FILTER DIGITAL MIXER (ADC) 22 23 DC-CANCELLATION FILTER DATAO BCK WS DATAI 18 13 16 L3-BUS/ I2C-BUS INTERFACE DIGITAL INTERFACE 17 VINR2 PGA PGA VINL1 VADCP VSSD 19 14 15 21 DIGITAL MIXER (DAC) DSP FEATURES 12 VINR1 IPSEL STATUS QMUTE L3MODE L3CLOCK L3DATA STATIC SYSCLK INTERPOLATION FILTER 20 NOISE SHAPER DAC VOUTL DAC 26 24 25 VDDA(DAC) 28 Vref Fig.1 Block diagram. 2000 Jul 31 TEST1 6...

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NXP Semiconductors Product specification Audio CODEC 7 UDA1342TS PINNING SYMBOL PIN TYPE DESCRIPTION VSSA(ADC) 1 analog ground pad ADC analog ground VINL1 2 analog input pad ADC input left 1 VDDA(ADC) 3 analog supply pad ADC analog supply voltage VINR1 4 analog input pad ADC input right 1 VADCN 5 analog pad ADC reference voltage N VINL2 6 analog input pad ADC input left 2 VADCP 7 analog pad ADC reference voltage P VINR2 8 analog input pad ADC input right 2 IPSEL 9 5 V tolerant digital input pad channel select input: input left 1 and right 1 or input left 2 and right 2 VDDD 10 digital supply pad...

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NXP Semiconductors Product specification Audio CODEC UDA1342TS 8.2 handbook, halfpage The analog front-end of the UDA1342TS consists of two stereo ADCs with a programmable gain stage (gain from 0 to 24 dB with 3 dB steps) which can be controlled via the L3-bus/I2C-bus interface. 28 Vref VSSA(ADC) 1 27 VSSA(DAC) VINL1 2 VDDA(ADC) 3 ADC analog front-end 26 VOUTL 8.2.1 25 VDDA(DAC) VINR1 4 VADCN 5 In applications in which a 2 V (RMS) input signal is used, a 15 kΩ resistor must be used in series with the input of the ADC (see Fig.3). This forms a voltage divider together with the internal ADC resistor...

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NXP Semiconductors Product specification Audio CODEC 8.2.2 UDA1342TS DOUBLE DIFFERENTIAL MODE 8.6 Mute Since the UDA1342TS is equipped with two stereo ADCs, these two pairs of stereo ADCs can be used to convert a single stereo signal to a signal with a higher performance by using the ADCs in the double differential mode. Muting the DAC will result in a cosine roll-off soft mute, using 32 × 32 = 1024 samples in the normal mode: this results in 24 ms at fs = 44.1 kHz. The cosine roll-off curve is illustrated in Fig.4. This mode and the input signals, being channel 1 or 2 as input to the double...

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NXP Semiconductors Product specification Audio CODEC UDA1342TS to digital interface output handbook, full pagewidth from decimation filter VOLUME AND MUTE master from digital interface input DE-EMPHASIS VOLUME AND MUTE BASS BOOST AND TREBLE + + VOLUME AND MUTE to interpolation filter MGT019 Fig.5 Digital mixer (DAC). 8.8 Noise shaper 8.10 The 5th-order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal...

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NXP Semiconductors Product specification Audio CODEC 8.11 UDA1342TS Sampling speed Important: in the double speed mode an input signal of 0 dB is allowed, but in the quad speed mode the input signal must be limited to −6 dB to prevent the system from clipping. The UDA1342TS operates with sample frequencies from 16 to 110 kHz. This range holds for the CODEC as a whole. The DAC part can be configured in the L3-bus and I2C-bus mode to accept 2 times and even 4 times the data speed (e.g. fs is 96 or 192 kHz), but in these modes not all of the features can be used. Some examples of the input oversampling...

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