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Micrel, Inc. MIC5162
June 2009 9 M9999-061509
Where I_source is the average source current. Power dissipation for the low-side MOSFET is as follows:
WCCJA260150°-°=è
PD = VTT × I_SINK
WCJA/45°=è
Where I_sink is the average sink current.
This shows that our total thermal resistance must be better than 45°C/W. Since the total thermal resistance is a combination of all the individual thermal resistances, the amount of heat sink required can be calculated as follows:
In a typical 3A peak SSTL_2 circuit, power considera-tions for MOSFET selection would occur as follows.
PD = (VDDQ -VTT) × I_SOURCE
PD = (2.5V -1.25V) × 1.6A
èSA = èJA - (èJC + èCA)
PD = 2W
In our example:
This typical SSTL_2 application would require both high-side and low-side N-Channel MOSFETs to be able to handle 2 Watts each. In applications where there is excessive power dissipation, multiple N-Channel MOSFETs may be placed in parallel. These MOSFETs will share current, distributing power dissipation across each device.
()CWCWCSA°+°-°=5.0/5.1/45è
WCSA/45°=è
In most cases, case-to-sink thermal resistance can be assumed to be about 0.5°C/W.
The SSTL termination circuit for our example, using 2 D-pack N-Channel MOSFETs (one high side and one on the low side) will require at least a 43°C/W heat sink per MOSFET. This may be accomplished with an external heat sink or even just the copper area that the MOSFET is soldered to. In some cases, airflow may also be required to reduce thermal resistance.
The maximum MOSFET die (junction) temperature limits maximum power dissipation. The ability of the device to dissipate heat away from the junction is specified by the junction-to-ambient (èJA) thermal resistance. This is the sum of junction-to-case (èJC) thermal resistance, case-to-sink (èCS) thermal resistance and sink-to-ambient (èSA) thermal resistance;
MOSFET Gate Threshold
èJA = èJC + èCS + èSA
N-Channel MOSFETs require an enhancement voltage greater than its source voltage. Typical N-Channel MOSFETs have a gate-source threshold (VGS) of 1.8V and higher. Since the source of the high side N-Channel is connected to VTT, the MIC5162 VCC pin requires a voltage equal to or greater than the VGS voltage. For example, our SSTL_2 termination circuit has a VTT voltage of 1.25V. For an N-Channel that has a VGS rating of 2.5V, the VCC voltage can be as low as 3.75V. With an N-Channel that has a 4.5V VGS, the minimum VCC required is 5.75V. Although these N-Channels are driven below their full enhancement threshold, it is recommended that the VCC voltage has enough margin to be able to fully enhance the MOSFETs for large signal transient response. In addition, low gate thresholds MOSFETs are recommended to reduce the VCC requirements.
In our example of a 3A peak SSTL_2 termination circuit, we have selected a D-pack N-Channel MOSFET that has a maximum junction temperature of 150°C. The device has a junction-to-case thermal resistance of 1.5°C/Watt. Our application has a maximum ambient temperature of 60°C. The required junction-to-ambient thermal resistance can be calculated as follows:
DAJJAPTT-=è
Where TJ is the maximum junction temperature, TA is the maximum ambient temperature and PD is the power dissipation.
In our example:
DAJJAPTT-=è
