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Micrel, Inc. MIC2593
September 2008 19 M9999-092208
Status Register, Slot B (STATB)
8-Bits, Read-Only
Status Register, Slot B (STATB)
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
read-only read-only read-only read/write read/write read/write read/write read/write
FAULTB MAINB VAUXB VAUXBF 12MVBF 12VBF 5VBF 3VBF
Bit(s) Function Operation
FAULTB FAULT Status, Slot B 1 = /FAULTB pin asserted
(/FAULTB pin is LOW)
0 = /FAULTB pin de-asserted
(/FAULTB pin is HIGH)
See Notes 1 and 2
MAINB MAIN Enable Status, Slot B Represents the actual state (on/off) of the four Main
Power outputs for Slot B (+12V, –12V, +5V and +3.3V)
1 = Main Power ON
0 = Main Power OFF
VAUXB VAUX Enable Status, Slot B Represents the actual state (on/off) of the Auxiliary
Power output for Slot B
1 = AUX Power ON
0 = Main Power OFF
VAUXBF Overcurrent Fault: VAUXB supply B 1 = Fault, 0 = No fault
12MVBF Overcurrent Fault: –12V supply B 1 = Fault, 0 = No fault
12VBF Overcurrent Fault: +12V supply B 1 = Fault, 0 = No fault
5VBF Overcurrent Fault: 5V supply B 1 = Fault, 0 = No fault
3VBF Overcurrent Fault: 3V supply B 1 = Fault, 0 = No fault
Power-Up Default Value: 0000 0000b = 00h
Command_Byte Value (R/W): 0000 0101b = 05h
The power-up default value is 00h. Both slots are disabled upon power-up, i.e., all supply outputs are off. In response to an
overcurrent fault condition, writing a logical 1 back into the active (or set) bit position will clear the bit and de-assert /INT. The
status of the /FAULTB pin is not affected by reading the Status Register or by clearing active status bits.
Note 1. If FAULTB has been set by an overcurrent condition on one or more of the MAIN outputs, the ONB input must go LOW to reset FAULTB.
If FAULTB has been set by a VAUXB overcurrent event, the AUXENB input must go LOW to reset FAULTB.
If an overcurrent has occurred on both a MAIN output and the VAUX output of slot B, both ONB and AUXENB of the slot must go low to
reset FAULTB.
Note 2. Neither the FAULTB bit nor the /FAULTB pin is active when the MIC2593 power paths are controlled by the System Management
Interface. When using SMI power path control, AUXENB and ONB pins for that slot must be tied to GND.
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