MIC2310: Single-FET, Constant Power-Limit Hot Swap Controller - Micrel - #29

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Micrel, Inc. MIC2310 July 2008 29 M9999-070108-A Open LOADSENSE Detector Trips CB In order to protect the system from the result of an open LOADSENSE pin, the controller incorporates an open LOADSENSE detection scheme. An open LOADSENSE pin could result in the effective primary OC detection threshold being at an unsafe level. The timing diagram in Figure 15 describes the operation of this function. With the applied VCC supply high such that the internal VREG voltage is above the controller’s VVREG(UVLOH) threshold voltage, an elapsed POR timer, and with the application of an ENABLE LOW-to-HIGH transition, the GATE drive circuitry is enabled and the GATE voltage begins to rise. As the external MOSFET turns ON, the SOURCE voltage begins to rise also. Normally, the LOADSENSE voltage would rise with the SOURCE voltage. However, if the LOADSENSE pin is open, the LOADSENSE voltage will remain at a lower voltage due to the load of other internal circuitry. An open LOADSENSE pin is detected by comparing the voltage at the SOURCE pin to the voltage at the LOADSENSE pin. Once the voltage at the SOURCE pin differs from the voltage at the LOADSENSE pin by VTHLOADSENSE, a circuit breaker is tripped, the GATE drive circuitry is disabled, the GATE fault-mode pull-down current sink is enabled, and the DISCH output goes high. This circuit breaker can be reset, such that the GATE drive circuitry can be re-enabled, by either a HIGH-to-LOW transition on ENABLE or turning off the VCC supply voltage to the controller such that VREG falls below the controller’s VVREG(UVLOL) threshold voltage. VCC & VREG ENABLE GATE VOUT ILOAD PWRGD LOADSENSE DISCH VVREG(UVLOL) VGSPGH VPGH tPOR VVREG(UVLOH) VTHLOADSENSE LOADSENSE OPEN VVREG(UVLOH) LOADSENSE CONNECTED tPOR Figure 15. Open LOADSENSE Detector Trips CB