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Questa ADMS

Questa ADMS
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Analog-Digital Mixed-Signal Simulator Analog/Mixed-Signal Verification Questa ADMS D A T A S H E E T FEATURES AND BENEFITS: ■ System-level design and architectural exploration ■ Questa user interface is familiar to digital design and verification engineers ■ Comprehensive digital, mixed-signal, transistor-level, and back-annotation language support ■ Five high-performance simulation engines ■ Extends Verilog-AMS to include SystemVerilog assertions Questa ADMS is the de facto industry standard for the creation and verification of complex analog and mixed-signal designs. Mixed-Signal Simulator for Modern Design Questa® ADMS extends the Mentor Graphics® Questa verification environment across the digital/analog divide. Design and verification engineers use Questa ADMS to develop and prove complex analog and mixed-signal designs. Questa ADMS combines five high-performance simulation engines in one efficient tool and supports every major electronic simulation language and exchange standard. A Flexible Mixed-Signal Strategy System-level verification of modern SoC designs is mandatory because of the high cost of respins. But system-level verification presents a dilemma. Simulating with only digital models is fast but inaccurate, and simulating with only transistor level models is too slow. A common verification strategy mixes and matches abstract models and detailed models, using the appropriate simulation algorithm for each portion of the design hierarchy. A different configuration may be used for each test point. This checkerboard strategy optimizes performance while maintaining accuracy for decisive criteria, but it demands flexibility along several dimensions—simulation engine, design language, module configuration, and overall EDA flow. w w w. m e nto r. co m ■ Bind SystemVerilog to Verilog-AMS modules, VHDL architectures, and SPICE sub-circuits ■ Mixed-signal extensions for UPF and UVM ■ Wreal (wire-real) support for real-number modeling in SystemVerilog and Verilog-AMS ■ EZwave mixed-signal waveform viewer and analysis tool ■ Integrated with Mentor Pyxis Schematic and Cadence Virtuoso tools for traditional analog flows

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2 Verification across the A-D Boundary Questa ADMS extends the advanced verification features familiar to digital designers to the mixed-signal world. Design Languages and Exchange Formats The Questa ADMS environment is language neutral so you can combine VHDL-AMS, Verilog-AMS, VHDL, Verilog, SystemVerilog SPICE, and SystemC in a single design. You can use either SPICE or an HDL at the testbench level. Questa ADMS supports both SDF, for back-annotation of timing data to digital library modules, and DSPF, for backannotation of parasitics in full customer design. Questa ADMS supports the...

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3 UVM and UPF Extensions Questa ADMS supports using the Universal Verification Methodology (UVM) with a mixed-signal design under test. A library of analog interface sources and probes, called O-SRC and O-PRB, extend the UVM for analog stimulus and measurement to the monitor/driver/ responder level. The O-SRC and O-PRB interface components range in complexity from the simplest voltage measurement and waveform generator to complex waveform extraction. Mixed-signal extensions to the Unified Power Format (UPF) allows verification engineers to connect power supply pins to power supplies that...

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4 EZwave Waveform Processor Questa ADMS offers the EZwave™ waveform processor to supplement the standard Questa viewer. EZwave provides the additional features necessary to display and analyze a mixture of RF, low-frequency baseband analog, and digital signals. It manipulates data in both the frequency and time domains. Smith charts, eye diagrams, FFT with sophisticated windowing, or signal-to-noise calculation are just some of the built-in features. Integration in Standard Design Flows Questa ADMS provides a stand-alone flow that extends the familiar Questa environment for integrated...

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5 Questa Questa combines high performance and high capacity with the code coverage and debugging capabilities required to simulate larger blocks and systems. Comprehensive support of SystemVerilog, VHDL, and SystemC provides a solid foundation for single and multi-language design verification environments. Eldo Classic The Eldo Classic analog kernel is the simulator of choice for IC silicon vendors and fabless design houses. Eldo Classic has been used to verify and successfully fabricate thousands of ICs. It is the absolute, golden, signoff reference for verification engineers and designers...

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6 such as LSF or Sun Grid and even with proprietary dispatching tools. Because the simulations run entirely in parallel, productivity scales linearly with the number of CPUs available. Checkpoint and Restart Questa ADMS allows the designer to save a checkpoint image of an ongoing simulation at any time. Then later, the same simulation can be restarted on the same or a different machine. It is even possible to change parameters before restart or to present a different set of test vectors to the restarted simulation. A single simulation can be executed until initialization is complete, and...

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simultaneously with the baseband part—and do it against a deadline. With Questa ADMS, you can see improvements of two or three orders of magnitude over less agile simulators when tested on mixed-signal RF designs with typical baseband-to-carrier freguency ratios. Fast Development of AMS Models Behavioral models in the AMS languages are an indispensable weapon in the mixed-signal verification arsenal, but AMS language modeling can be time- consuming. The interactive AMS Modeling Cookbook for VHDL-AMS and Verilog-A combines technigues for mixed- signal behavioral modeling that give the...

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