MEN CompactPCI

F12 – 3U CompactPCI

®

MPC5200 SBC

32-bit/33-MHz cPCI system slot, 4 HP

MPC5200/384 MHz

FPGA 12,000 LEs (approx. 144,000 gates)

Up to 256 MB on-board DDR SDRAM

Up to 8 MB boot Flash, NAND Flash

Up to 2 MB SRAM, 16MB graphics memory

Dual Fast Ethernet, COM, USB (front)

Dual CAN controller

FPGA for user-defined I/O functions

MENMON

™

BIOS for PowerPC

cards

-40 to +85°C with qualified components CPU

N FPGA-controlled
N Accessible via I/O connector
N PowerPC
® , MPC5200, up to 400MHz
N PIO mode 0 support
N Physical interface at front panel using SA-Adapter

Memory I/O

™ via 10-pin ribbon cable on I/O connector
N 2x16KB L1 data and instruction cache intgrated in MPC5200
N USB
N One USB 1.1 port
N RS232..RS485, isolated or not: for free use in system (e. g. cable to front)
N Up to 256MB SDRAM system memory
N Series A connector at front panel
N Soldered, DDR
N OHCI implementation
N Data rates up to 115kbits/s
CompactPCI N 64MHz memory bus frequency
N Data rates up to 12Mbits/s
N 16-byte transmit/receive buffer
N Up to 1GB soldered NAND Flash (depending on chip availability), FPGA-controlled
N Ethernet
N Handshake lines: CTS, RTS; DCD, DSR, DTR; RI
N Two 10/100Base-T Ethernet channels
N CAN bus
N Up to 8MB boot Flash
N 2 RJ45 or 1 D-Sub connector at front panel
N Two CAN bus channels
N Up to 2MB GoldCap-backed SRAM, or: up to 128KB non-volatile FRAM
N Note: 2nd Ethernet channel will be operable in Q1/2007; through update of FPGA.
N 2.0 A/B CAN protocol
N Data rates up to 1 Mbit/s
N Serial EEPROM 8kbits for factory settings
N One RS232 UART (COM1)
N Connection via on-board industrial connectors
N Up to 16MB additional SDRAM, connected to FPGA, e.g. for video data
N RJ45 or D-Sub connector at front panel
N External transceivers using SA-Adapters
™ N Data rates up to 115kbits/s
N GPIO

Mass Storage

N 512-byte transmit/receive buffer
N 36 GPIO lines
N Parallel IDE (PATA)
N Handshake lines: CTS, RTS
N FPGA-controlled
N One IDE port via 44-pin on-board connector
N One UART (COM10)
N Connection via on-board I/O connector
N Further I/O depending on FPGA configuration

Front Connections (Standard)

N One USB 1.1 (Series A)
N Two Ethernet (RJ45)
N One RS232 UART (RJ45)

FPGA

N Standard factory FPGA configuration:
N Main bus interface
N 16Z070_IDEDISK - IDE contr. for NAND Flash
N 16Z043_SDRAM - SDRAM controller (16 MB)
N 16Z023_IDE_NHS - IDE controller (PIO mode 0; non-hot-swap)
N 16Z025_UART - UART controller (controls COM10)
N 16Z034_GPIO - GPIO controller (40 lines, 5 IP cores)
N The FPGA offers the possibility to add custmized I/O functionality. See website.

Miscellaneous

N Real-time clock with GoldCap backup
N Power supervision and watchdog
N Reset button, GPIO-controlled
N Three user LEDs, GPIO-controlled; 1 FPGA power status LED

CompactPCI

Bus

N Compliance with CompactPCI
® Core Specification PICMG 2.0 R3.0
N System slot
N 32-bit/33-MHz PCI-to-PCI bridge
N V(I/O): +3.3V (+5V tolerant)

PXI™

N 4 trigger lines compliant with PXI
™ Spec. R1.0

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