MEN CompactPCI

F13 – 3U CompactPCI

®

MPC8540 SBC

32-bit/33-MHz cPCI system slot, 4 HP

MPC8540, 800MHz (PowerQUICC

™

III)

FPGA 12,000 LEs (approx.144,000 gates)

Up to 2 GB DDR DRAM (SO-DIMM)

NAND Flash

2 Gigabit/1 Fast Ethernet (RJ45 on front)

1 COM (RJ45 on front)

FPGA for user-defined I/O functions

MENMON

™

BIOS for PowerPC

cards CPU Front Connections (Standard) Miscellaneous

N PowerPC
® N Three Ethernet (RJ45)
N Real-time clock with GoldCap backup
N MPC8540 PowerQUICC
™ III
N One RS232 UART (RJ45)
N Power supervision and watchdog
N 800MHz (666..833MHz optional)

FPGA

N Reset button, GPIO-controlled
N e500 PowerPC
® core with SPE APU and MMU
N Standard factory FPGA configuration:
N Three user LEDs, GPIO-controlled; 1 FPGA power status LED
N Integrated Northbridge and Southbridge
N Main bus interface
N High memory bandwidth
N 16Z070_IDEDISK – IDE controller for NAND Flash

CompactPCI

Bus Memory

N Compliance with CompactPCI
® Core Specification PICMG 2.0 R3.0
N 2x32KB L1 data and instruction cache, 256KB L2 cache/SRAM integrated in MPC8540
N 16Z043_SDRAM – SDRAM controller (16MB)
CompactPCI N 16Z023_IDE_NHS –IDE controller (PIO mode 0; non-hot-swap)
N System slot
N Up to 2GB SDRAM system memory
N 32-bit/33-MHz PCI-to-PCI industrial bridge
N One SO-DIMM slot for SDRAM modules
N 16Z025_UART – UART controller (controls COM10)
N V(I/O): +3.3V (+5V tolerant)
N DDR2100 with or without ECC

PXI™

N 133MHz memory bus frequency
N 16Z034_GPIO – GPIO controller (40 lines, 5 IP cores)
N Four trigger lines compliant with PXI
™ Specification R1.0
N Up to 1GB soldered NAND Flash (depending on chip availability), FPGA-controlled
N The FPGA offers the possibility to add customized I/O functionality. See website.
N 8MB boot Flash
N 32KB non-volatile FRAM
N Up to 16MB additional SDRAM, FPGA-controlled, e.g. for video data
N Serial EEPROM 4kbits for factory settings

Mass Storage

N Parallel IDE (PATA)
N One IDE port via 44-pin on-board connector
N FPGA-controlled
N PIO mode 0 support

I/O

N Three Ethernet channels
N Two 10/100/1000Base-T Ethernet channels
N One 10/100Base-T Ethernet channel
N Three RJ45 connectors at front panel
N Two on-board LEDs to signal LAN Link and Activity
N One RS232 UART (COM1)
N One RJ45 connector at front panel
N Data rates up to 115kbits/s
N 16-byte transmit/receive buffer
N Handshake lines: CTS, RTS
N One UART (COM10)
N FPGA-controlled
N Accessible via I/O connector
N Physical interface at front panel using SA-Adapter
™ via 10-pin ribbon cable on I/O connector
N RS232..RS485, isolated or not: for free use in system (e. g. cable to front)
N Data rates up to 115kbits/s
N 16-byte transmit/receive buffer
N Handshake lines: CTS, RTS; DCD, DSR, DTR; RI
N GPIO
N 36 GPIO lines
N FPGA-controlled
N Connection via on-board I/O connector
N Further I/O depending on FPGA configuration

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