89LV1632 - SRAM, 16 Mb (512kb x 32) - 12 Pages

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89LV1632 - SRAM, 16 Mb (512kb x 32)

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89LV1632 16 Megabit (512K x 32-Bit) Low Voltage MCM SRAM 16 Megabit (512k x 32-bit) SRAM MCM CS 1-4 Address OE, WE Power 4Mb SRAM 4Mb SRAM 4Mb SRAM 4Mb SRAM I/O 8-15 I/O 16-23 I/O 24-31 Ground 89LV1632 MCM Memory I/O 0-7 Logic Diagram FEATURES: DESCRIPTION: • Four 512k x 8 SRAM die • RAD-PAK® Technology radiation-hardend against natural space radiation • Total dose hardness: - > 100 krad (Si), depending upon space mission • Excellent Single Event Effects: - SEL > 101MeV-cm2/mg - SEU threshold = 3 MeV-cm2/mg - SEU saturated cross section: 6E-9 cm2/bit • Package: 68-pin quad flat package • Completely static memory - no clock or timing strobe required • Fast Access Time: • -20, 25, 30 ns Access Times • Internal bypass capacitor • High-speed silicon-gate CMOS Technology • 3.3 V ± 10% power supply • Equal address and chip enable access times • Three-state outputs • All inputs and outputs are TTL compatible Maxwell Technologies’ 89LV1632 high-performance 16 Megabit Multi-Chip Module (MCM) Static Random Access Memory features a greater than 100 krad(Si) total dose tolerance, depending upon space mission. The four 4-Megabit SRAM die and bypass capacitors are incorporated into a high-reliable hermetic quad flat-pack ceramic package. With high-performance silicon-gate CMOS technology, the 89LV1632 reduces power consumption and eliminates the need for external clocks or timing strobes. It is equipped with output enable (OE) and four byte chip enables (CS1 - CS4) inputs to allow greater system flexibility. When OE input is high, the output is forced to high impedance. Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package.It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or a space mission. In a GEO orbit, RAD-PAK® packaging provides greater than 100 krad(Si) total radiation dose tolerance. This product is available with screening up to Maxwell Technologies selfdefined Class K. 08.07.07 Rev 4 (619) 503-3300 - Fax: (619) 503-3301 - www.maxwell.com All data sheets are subject to change without notice 1 ©2007 Maxwell Technologies. All rights reserved.

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89LV1632 16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM TABLE 1. PINOUT DESCRIPTION PIN SYMBOL DESCRIPTION 34-28, 42-36, 62-64, 7, 8 A0-A18 65 WE WriteEnable 66 OE Output Enable 3-6 CS1 - CS4 Chip Enable 43-46, 48-51,53-56, 58-61, 9-12, 14-17, 19-22, 24-27 I/O0-I/O31 Data Input/Output 2, 67, 68 NC No Connection 1, 18, 35, 52 VCC +3.3V Power Supply 13, 23, 47, 57 VSS Ground Address Enable Memory TABLE 2. 89LV1632 ABSOLUTE MAXIMUM RATINGS (VOLTAGE REFERENCED TO VSS = 0V) PARAMETER SYMBOL UNITS -0.5 +4.6 V VIN, VOUT -0.5 VCC+0.5 V 42 Voltage Relative to VSS for Any Pin Except VCC MAX VCC Power...

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16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM 89LV1632 TABLE 4. 89LV1632 DELTA LIMITS PARAMETER VARIATIONL ICC +10% of stated value in table 5 ISB +10% of stated value in table 5 ISB1 +10% of stated value in table 5 ILI +10% of stated value in table 5 TABLE 5. 89LV1632 DC ELECTRICAL CHARACTERISTICS (VCC = 3.3+ 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED) SYMBOL TEST CONDITIONS PARAMETER SUBGROUPS MIN TYP MAX UNITS ILI VIN = 0 to VCC 1, 2, 3 -8.0 -- +8.0 uA Output Leakage Current ILO CS = VIH, VOUT = VSS to VCC 1, 2, 3 -8.0 -- +8.0 uA Operating Current : -20 -25 -30 ICC Min. Cycle,...

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89LV1632 16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM TABLE 6. 89LV1632 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 3.3+ 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED) PARAMETER MIN TYP MAX UNITS Output Timing Measurement Reference Level -- -- 1.5 V Input Rise/Fall Time -- -- 3.0 ns Input Timing Measurement Reference Level -- -- 1.5 V TABLE 7. 89LV1632 AC CHARACTORISTICS FOR READ CYCLE (VCC = 3.3+ 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED) PARAMETER SYMBOL SUBGROUPS Read Cycle Time -20 -25 -30 tRC 9, 10, 11 Address Access Time -20 -25 -30 tAA Chip Select Access Time -20...

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89LV1632 16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM TABLE 7. 89LV1632 AC CHARACTORISTICS FOR READ CYCLE (VCC = 3.3+ 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED) PARAMETER SYMBOL SUBGROUPS Output Hold from Address Change -20 -25 -30 tOH 9, 10, 11 Chip Select to Power Up Time -20 -25 -30 TPU Chip Select to Power DownTime -20 -25 -30 TPD MIN TYP MAX 3 5 6 ---- ---- ---- 0 0 0 ---- ---- 10 15 20 UNITS ---- ns ns 9, 10, 11 ns 9, 10, 11 CS WE OE MODE I/O PIN SUPPLY CURRENT H X1 X1 Not Select High-Z ISB, ISB1 L H H Output Disable High-Z ICC L H L Read DOUT ICC L X1 Write DIN Memory TABLE...

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16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM 89LV1632 TABLE 9. 89LV1632 AC CHARACTORISTICS FOR WRITE CYCLE (VCC = 3.3+ 10%, TA = -55 TO +125 ° C, UNLESS OTHERWISE NOTED) PARAMETER SUBGROUPS Address Valid to End of Write -20 -25 -30 tAW 9, 10, 11 Write Pulse Width (OE High) -20 -25 -30 tWP Write Pulse Width (OE Low) -20 -25 -30 tWP1 Write Recovery Time -20 -25 -30 tWR Write to Output High-Z -20 -25 -30 tWHZ Data to Write Time Overlap -20 -25 -30 tDW Data Hold from Write Time -20 -25 -30 tDH End Write to Output Low-Z -20 -25 -30 tOW MIN TYP MAX 14 15 17 ---- ---- 14 15 17 ---- ---- 20 25 30...

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16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM 89LV1632 FIGURE 1. AC TEST LOADS + 3.3V Memory FIGURE 2. TIMING WAVEFORM OF READ CYCLE (1) (ADDRESS CONTROLLED) FIGURE 3. TIMING WAVEFORM OF READ CYCLE (2) (WE = VIH) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 08.07.07 REV 4 All data sheets are subject to change without notice 7 ©2007 Maxwell Technologies. All rights reserved.

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16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM 89LV1632 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage conditions, tHZ (max) is less than tLZ (min) both for a given device and from device to device. 5. Transition is measured +200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS = VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications,...

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