TADMVC2G52 SONET/SDH 155/622/2488 Mbits/s Add/Drop Data Interface - LSI Logic - #1

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TADMVC2G52 SONET/SDH 155/622/2488 Mbits/s Add/Drop Data Interface Product Brief Features n Mix Transmission convergence and SONET/SDH terminal/ADM functionality for linear and ring networks. n Virtual concatenation with dynamic pipe-sizing. n Versatile IC supports 155/622/2488 Mbits/s SONET/SDH interface solutions for packet over n SONET (POS), packet over fiber (POF), or asynchronous transfer mode (ATM) applications. n Low-power 1.6/3.3 V operation. SONET/SDH Interface n Termination of quad STS-3/STM-1, quad STS-12/STM-4, or single STS-48/STM-16. n Supports overhead processing for transport and path overhead bytes. n Optional insertion and extraction of overhead bytes via serial overhead interface. n STS pointer processing to align the receive frame to the system frame. n STS-1 granularity cross connect between receive, mate, STM, and data payloads. n Support for 1+1 and 1:1 linear networks; UPSR and BLSR ring networks. n Full path termination and SPE extraction/insertion. n SONET/SDH compliant condition and alarm reporting. n Handles all concatenation levels of STS-3c to STS-48c (in multiples of 3: e.g., 3c, 6c, 9c, etc.). n Built-in diagnostic loopback modes. n Compliant with the following Telcordia n Technologies®, ANSI, and ITU standards: — GR-253 CORE: SONET Transport Systems: Common Generic Criteria. — ITU-T G.707: Network Node Interface for the Synchronous Digital Hierarchy. — ITU-T G.803: Architecture of Transport Networks Based on the Synchronous Digital Hierarchy. — T1.105: SONET-Basic Description including Multi plex Structure, Rates, and Formats. — T1.105.02 SONET-Payload Mappings. — T1.105.03 SONET-Jitter at Network Interfaces. — T1.105.06 SONET Physical Layer Specifications. — T1.105.07 SONET-Sub-STS-1 Interface Rates and Formats Specification. — ITU-T I.432: B-ISDN User-Network Interface- Physical Layer Specification. — IETF RFC 2615: PPP over SONET/SDH. — IETF RFC 1661: The Point-to-Point Protocol (PPP). — IETF RFC 1662: PPP in HDLC-like Framing. Data Processing n Provisionable data engine supports payload insertion/extraction for PPP, ATM, or HDLC streams. n Extraction and insertion of DS3 frames containing HDLC or ATM datastreams for up to 16 channels. n Integrated UTOPIA Level 2 and Level 3 compatiblephysical layer interface for packets or ATM cells. n Provides/supports internal E3 mapping. n Supports DS3/PLCP and clear channel DS3 mapping. n Insertion and extraction of up to 16 separate data channels. n Direct cell/packet over fiber interface device. n Compliant with ATM forum, ITU standards, and IETF standards. n Supports generic framing procedure (GFP) protocol. Interfaces n Enhanced UTOPIA interface for cell and packet transfer (PLATO). n Built-in redundant STS/STM backplane interface using 622 MHz LVDS technology. n Mate-to-mate backplane interface using 622 MHz LVDS technology for 1+1, 1:1, BLSR, and UPSR network support. n Optional 78 MHz bus (32-bit) for STS/STM interface.IEEE® 1149.1 port with BIST, scan, and boundry scan. Microprocessor Interface n Up to 66 MHz synchronous. n 16-bit address and 16-bit data interface. n Synchronous or asynchronous modes available. n Configurable to operate with most commercial microprocessors