Hypermapper ™ II 622/155 Mbits/s SDH/SONET x DS3/E3/DS1/E1/DS0 Mapper - LSI Logic - #1

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Hypermapper ™ II 622/155 Mbits/s SDH/SONET x DS3/E3/DS1/E1/DS0 Mapper Product Brief Hypermapper II defines a family of highly versatile, system-on-a-chip (SOC) solutions which integrate SDH/SONET section, line, path, and tributary termination functions with M13/E13 multiplex functions, grooming/time slot assignment, and primary rate (DS1/E1/J1) framing. The device interfaces to an STS-3/STM-1, or to an STS-12/STM-4 signal supporting modular growth in terminal, add/drop, Enterprise WAN, or switching applications. The Hypermapper II family of devices provides a flexible solution for all STS-12/STM-4 , STS-3/STM-1 and STS-1/STM-0 termination applications for point-to-point scenarios and ring applications. For tributary shelf applications Hypermapper II devices can terminate up to 336 DS1/J1 or 252 E1 links, and provide an array of possible mappings to/from SDH/SONET. A single device fully supports MSP 1+1 and can terminate up to forty eight DS3/E3/STS-1 signals, or up to 336/252 DS1/J1/E1 signals. Flexible performance monitoring is supported for all SDH/SONET and PDH interfaces. A single Hypermapper II can also function as an STS- 12/STM-4 or STS-3/STM-1 add/drop multiplexer by terminating up to three STS-1/STM-0 channels or one AU-4 channel and, through use of internal pointer processors, can forward any nonterminated channels. Hypermapper II can terminate a full STS-12/STM-4 payload F e a t u r e s n Signal interfaces: — x1 STS-12/STM-4 or STS-3/STM-1 port (+1 protection port at same rate). — Up to x 48 STS-1/DS3/E3 interfaces. — DS0 interfaces include a 19.44 MHz parallel system bus; 16 MHz serial concentration highway; 51.84 MHz network serial multiplexed interfaces. n SONET/SDH functionality: — Multiplexes/demultiplexes any one of the following: — Twelve STS-1 signals to/from a STS-12 signal. — Three STS-1 signals to/from an STS-3 signal. — Four STM-1 (AU-4 or 3xAU-3) signals to/from an STM-4 signal. — Three VC-3/TUG-3 signals to/from an STM-1 (AU-4 or 3xAU-3) signal. — Provides separate protection input for support of 1:1 and 1 + 1. — STS3c/STM1c capability for concatenated payload add/drop. — Full SONET/SDH compliant alarm reporting. n STS-1 line terminations supporting standard SPE mappings for sub-STS-1 payloads as well as DS3/E3 payloads. Provides STS-1 pointer interpretation/processing. n Pointer processors, which support an arbitrary mix of STS-1 and STS-3c tributaries, and SDH equivalents for pass-through from receiver to transmitter. n Virtual tributary mapping: — Maps DS1/E1/J1 into VT/TU containers as: DS1/J1 into VT1.5/TU-11/TU-12, E1 into VT2/TU-12. — Supports asynchronous, byte synchronous, and bit synchronous mappings. — Full monitoring/generation of low-order path overhead. n Test pattern generators/monitors for multiple signal rates. Support for a variety of test patterns as well as bit error injection. n M13 MUXes/DeMUXes provisionable for either M23 or C-bit parity mode. Full DS3 level alarm monitoring and generation on all twelve channels. n E13 MUXes/DeMUXes including E3-level performance monitoring. n Flexible multirate cross point interconnects for DS0, DS1/E1, DS3/E3, STS-1 signals between internal device blocks and between blocks and device I/O. n Protection for ATCA applications via a single ATCA backplane link n 4 x OC-3 Protection for backplane applications n Register compatibility to Ultramapper to support software reuse. n Typical Power Dissipation: < 4 Watts