Catalogue - MachXO Product Brief - Lattice Semiconductor

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Mixed-signal FPGA, FPGA software, Evaluation kit, FPGA, System-on-chip

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ECONFIGURABLE PLD

MachXO Family

Crossover Programmable Logic Devices

The MachXO™ family of non-volatile, infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for applications traditionally implemented using CPLDs or low-capacity FPGAs. The MachXO family combines an optimized Look-Up Table (LUT) fabric with Lattice's ispXP™ technology to provide the high pin-to-pin performance and instant-on associated with CPLDs, with the flexibility of FPGAs, all in a low-cost device.

The MachXO family offers a high pin-to-logic ratio that is ideal for glue logic, bus bridging, bus interfacing, power-up control and control logic. In addition, MachXO devices feature Lattice's exclusive sysCLOCK™ PLLs, sysMEM™ embedded memory blocks (EBRs) and high-performance

SRAM

Flash

I/Os. These features further facilitate the design of highspeed systems.

Designs for MachXO can easily be completed with Lattice's free ispLEVER® Starter design software.

MachXO Applications

Key Features and Benefits

■ Non-Volatile, Infinitely Reconfigurable

• Instant-on, powers up in less than lmS

• Single-chip, no external configuration memory

• Excellent design security, no bit stream to intercept

■ Performance to 3.5ns Pin-to-Pin

■ TransFR Technology Allows Simple Field Upgrades

■ Flexible LUT Architecture

• 256 to 2280 LUT4s

• 73 to 271 I/Os with extensive package options

• Density migration supported

■ Embedded and Distributed Memory

• Up to 27.6 Kbits sysMEM Embedded Block RAM

• Includes dedicated FIFO control logic

• Up to 7.7 Kbits distributed RAM

■ Flexible I/O Buffer

• Programmable sysIO™ buffer supports wide range of interfaces:

- LVCMOS 3.3/2.5/1.8/1.5/1.2

- LVTTL

- PCI*

- LVDS*, Bus-LVDS*, LVPECL*, RSDS*

■ sysCLOCK PLLs

• Up to two analog PLLs per device

• Clock multiply, divide and phase shifting

■ Sleep Mode Reduces Standby Power to <100uA

■ System Level Support

• IEEE Standard 1149.1 Boundary Scan

• Onboard 20MHz oscillator for configuration and user logic

• Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply

■ Broad Device Offering

• Commercial: 0 to 85°C (Tjcom)

• Industrial: -40 to 100°C (Tjind)

• AEC-Q100 qualified: -40 to 125°C (Tjauto)


		Bus Interface		Control Logic
		Bus Bridging		Signal Distribution
		Power and Reset		System Power-up
		Control		Management
		ASIC & FPGA		Power-up Sequencing
		Configuration		Data Conversion
		Memory Control		Chip Select
		Glue Logic		Chip Select

MachXO Configuration

MachXO devices include both Flash and SRAM technology to provide "instant-on" capabilities in a single low-cost device. At power-up, configuration data is transferred from Flash to SRAM cells in less than lmS. Both SRAM and Flash memory can be programmed from a JTAG port. This combination of SRAM and Flash enables easy field updates via Lattice's unique TransFR™ technology. MachXO devices have a security scheme that prevents readback and, by using Flash internally, Lattice eliminates bit stream snooping.

MachXO Device

On-chip Flash memory.

Control Logic



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(C	SRAf ontr	/1 Co ils D	nfigu evic	ratio : Op	n Bit rati	s n)	'i

Massively parallel wide data transfer provides snoop-proof SRAM configuration from Flash.

Use JTAG port (IEEE1532/1149.1) to configure SRAM or program Flash.

* MachXO1200 and 2280 devices only.

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