MachXO Product Brief - Lattice Semiconductor - (Version JPG) - Page n° 4 - PDF Catalogue | Technical Documentation

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Mixed-signal FPGA, Power management controller, FPGA software, Evaluation kit, FPGA

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TransFR - Easy Field Updates

MachXO devices include Lattice's exclusive Transparent Field Reconfiguration (TransFR) technology. TransFR technology allows logic to be updated in the field without interrupting system operation.

Thanks to its dual SRAM and Flash configuration space architecture, the MachXO requires less than 2mS to reconfigure, an order of magnitude lower than competing solutions. To change the logic configuration, simply program the Flash in the background while the logic functions normally. In a single command, Lattice's ispVM® software locks the I/Os, copies Flash to SRAM, allows the data state to be initialized and unlocks the pins. Your logic is upgraded instantly!

ispLEVER Development Tools

Lattice's ispLEVER development tools offer a comprehensive design environment for the MachXO architecture. ispLEVER tools include everything you need for design entry, synthesis, map, place & route, floorplanning, simulation, project management, device programming and more. Synthesis and simulation tools from industry leaders Mentor Graphics and Synplicity are included with ispLEVER.

Evaluation and Development Boards

Lattice offers a number of evaluation and development boards that provide a ready-made platform to evaluate the performance of the MachXO device, or aid in development of custom designs. Go to www.latticesemi.com/boards for more information.

ispLeverCORE™ Intellectual Property

Lattice offers an expanding portfolio of IP cores and reference designs to support easy integration of commonly used functions. For the MachXO this includes:

FLASH (Configuration 2)

......

Logic - SRAM (Configuration 1)

ispLever CORE

• PCI Master/Target

• 8-bit Microcontroller

• SDRAM Memory Controllers

• PC Controller For additional IP cores, go to www.latticesemi.com/ip.

Program Flash in background while logic functions

JTAG commands control I/O & logic states while Flash is copied to SRAM -Device is operational in <2mS

Device Selection Guide


Parameter	LCMXO256	LCMXO640	LCMXO1200	LCMXO2280
LUTs	256	640	1200	2280
Distributed RAM (Kbits)	2	6.1	6.4	7.7
Embedded Block RAM - EBR (Kbits)	-	-	9.2	27.6
Number of EBR Blocks	- 13
Vcc Voltage (V) Options	1.2V or 1.8/2.5/3.3V	1.2V or 1.8/2.5/3.3V	1.2V or 1.8/2.5/3.3V	1.2V or 1.8/2.5/3.3V
Number of PLLs	--12
Number of I/O Banks	1 2 1 4 1 8 1 8
Maximum Number of I/Os	78	159	211	271
Maximum Number of LVDS Pairs*	-	-	27	33
Packages & I/O Combinations 100-pin TQFP (14 x 14 mm)**	78	74	73	73
144-pin TQFP (20 x 20 mm)		113	113	113
100-ball csBGA (8 x 8 mm)	78	74
132-ball csBGA (8 x 8 mm)		101	101	101
256-ball ftBGA (17 x 17 mm)		159	211	211
324-ball ftBGA (19 x 19 mm)				271

* Number of LVDS outputs can be increased by emulating with external resistors. ** In the 100-pin TQFP package, designs can not migrate from LCMXO640 to 1200.

Applications Support

1-800-LATTICE (528-8423) (503) 268-8001 techsupport@latticesemi.com

iiiLattice

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ispLeverCORE, ispTRACY, ispVM, ispXP, MachXO, sysCLOCK, sysIO, sysMEM, and TransFR are either registered trademarks or trademarks of Lattice Order #: I0176D

Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

MachXO Product Brief - Lattice Semiconductor - #4

Mixed-signal FPGA, Power management controller, FPGA software, Evaluation kit, FPGA