Text version of the page

EXPANDED PROGRAMMABLE LOGIC DEVICES

Non-VolatileInstant-OnInfinitelyReconfigurable

Ultimate ispXP™ Flexibility ispXPLD 5256MX Block DiagramKey Features and Benefits

ispXPLD Product Brief - 30624 ispXPLD 5000MX

The ispXPLD™ 5000MX family represents a new class ofdevices from Lattice Semiconductor called eXpandedProgrammable Logic Devices (XPLDs). These devices arebuilt around a new building block, the Multi-Function Block (MFB). These blocks can be configured asSuperWIDE™ (136-input) logic, single- or dual-portmemory, FIFO, or CAM depending on the user’s application.This unparalleled PLD flexibility is combined with sysIO™interfaces for support of leading edge standards such asLVDS, HSTL, and SSTL, along with the more familiarLVCMOS standards. sysCLOCK™ PLLs allow easy clock management. ispXPLD 5000MX devices provide expandedin-system programming referred to as ispXP. As such,ispXPLD devices are non-volatile and infinitely reconfigurable. They can be programmed through anindustry standard IEEE 1532 interface or reconfiguredthrough the Lattice sysCONFIG™ interface. Devices are available to support 3.3, 2.5, and 1.8-volt power supplyoperation.

â– 

Flexible MFB Architecture

Multi Function Blocks are independentl Global Routing Pool ( GRP ) as lo g ic, sin p rovides flexible, deterministi c memor y , FIFO, or CA

Flexibility

? SuperWIDE Logic? Arithmetic support ? Single- or Dual-Port RAM ? Asynchronous FIFO ? Ternary CAM

â–  ( MFBs )

sysCLOCK PLLs

y programmable

? Multiply & divide? Clock shifting

g le- or dual-por t M routin g
â– 

sysIO Interfaces

I / O Bank I / O Bank 3

? LVTTL, LVCMOS 1.8, 2.5, 3.3: Programmable drivestrength; Flexible bus-maintenance; Hot-socketing? SSTL, HSTL ? GTL+, PCI-X, PCI 3.3, AGP-1X ? LVDS ? LVPECL

sysIO MFB MFB sysIO sysIO MFB sysIO MFB
â– 

Expanded In-System Programming (ispXP)

G loba l

? Instant-on capability? Single chip convenience ? ISP™ via IEEE 1532 Interface ? Infinitely reconfigurable via IEEE 1532 or sysCONFIGinterface? Security scheme

sysCLOCK PLL

Routin g

sysCLOCK PLL

Poo l

sysIO MFB MFB sysIO
â– 

High Speed Operation

sysI O sysIO

? 4.0ns pin-to-pin delays? 300 MHz f

MFB MFB
MAX

? Deterministictiming

I/O Bank 1 an a n I S P Por t
I/O Bank 2 â– 

Low Power Consumption

sysCLOCK PLLs

? Static power as low as 20mA? 1.8-volt core for low dynamic power

sysI O for ultra hi g h speed I/O s I S P Por t offers non-volatile, In-s y stem
â– 

Easy System Integration

pro g rammabilit y , and reconfi g urabilit y

? 3.3, 2.5 and 1.8-volt power supply operation? IEEE 1149.1 boundary scan testing ? Lead-free package options

via s y sCONFIG interface