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System Memory CAM Family Member Gates Macrocells kbit kbit PLLs t
PD t
S t
CO F
MAX Vcc ispXPLD 5256MV
75K 256 128 48 2 4.0ns 2.2ns 2.8ns 300MHz 3.3V ispXPLD 5512MV
150K 512 256 96 2 4.5ns 2.8ns 3.0ns 270MHz 3.3V ispXPLD 5768MV
225K 768 384 144 2 5.0ns 2.8ns 3.2ns 250MHz 3.3V ispXPLD 51024MV
300K 1024 512 192 2 5.2ns 3.0ns 3.7ns 250MHz 3.3V ispXPLD 5256MB
75K 256 128 48 2 4.0ns 2.2ns 2.8ns 300MHz 2.5V ispXPLD 5512MB
150K 512 256 96 2 4.5ns 2.8ns 3.0ns 270MHz 2.5V ispXPLD 5768MB
225K 768 384 144 2 5.0ns 2.8ns 3.2ns 250MHz 2.5V ispXPLD 51024MB
300K 1024 512 192 2 5.2ns 3.0ns 3.7ns 250MHz 2.5V ispXPLD 5256MC
75K 256 128 48 2 4.0ns 2.2ns 2.8ns 300MHz 1.8V ispXPLD 5512MC
150K 512 256 96 2 4.5ns 2.8ns 3.0ns 270MHz 1.8V ispXPLD 5768MC
225K 768 384 144 2 5.0ns 2.8ns 3.2ns 250MHz 1.8V ispXPLD 51024MC
300K 1024 512 192 2 5.2ns 3.0ns 3.7ns 250MHz 1.8V Family Member 208 PQFP 256 fpBGA* 484 fpBGA* 672 fpBGA* ispXPLD 5256MX – 141 – – ispXPLD 5512MX 149 193 253 – ispXPLD 5768MX – 193 317 – ispXPLD 51024MX – – 317 381 * fpBGA = Fine Pitch BGA (1.0mm ball pitch)

ispXPLD Product Brief - 30624 ispXPLD 5000MX Advanced Packaging ispXPLD 5000MV, 5000MB and 5000MC Family Attributes* ispXPLD 5000MX Family Package Options and Available I/Os

Packages are shown actual size. Dimensions refer to package body size.

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Copyright © 2004 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), ISP, sysCONFIG,sysIO, sysCLOCK, SuperWIDE, ispXP, and ispXPLD are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United Statesand/or other countries. Other product names used in this publication are for identification purposes only and may be trademarksof their respective companies. January 2004Order #: I0140B