Catalogue - ispMACH 4000 Product Brief - Lattice Semiconductor

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Software, Clock generator, FPGA software, Controller, System-on-chip

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IN-SYSTEM

HIGH PERFORMANCE ANfl inw POWER

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ispMACH 4000

The Industry's Fastest and Lowest Power CPLDs

New CPLD Architecture Couples Super-FAST Performance and Low Power

The ispMACH™ 4000 is the industry's fastest and lowest power ISP™ Complex Programmable Logic Device (CPLD) Family With a SuperFAST™ 2.5ns pin-to-pin delay and low dynamic power, the ispMACH 4000 Family is the ultimate solution for high performance systems.

The ispMACH 4000 family contains three separate sub-families, supporting 3.3V (ispMACH 4000V), 2.5V (ispMACH 4000B), and 1.8V (ispMACH 4000C).

Utilizing Lattice's latest generation E²CMOS® process technology, the ispMACH 4000 architecture combines the best features of Lattice's ispMACH4A and ispLSI® 2000 families and provides high speed, low dynamic power consumption, enhanced logic control, and flexible I/O.

The new ispMACH 4000 Family is fully supported by Lattice's easy-to-use and powerful ispLEVER® design software, plu^-a-wwl^range of popular third-party tools. Designing with igi»MAC\I 4000 devices is quick_and easviisine lead-iX^^syntRBSt^^anJ simulation toolsfmrnlVe^^l^s^ogr^,

ispMACH 4000 Block Diagram

Key Features and Benefits

■ SuperFAST Performance ^---.

I • 2.5 ns tpD Pir/-to-Pm Delajr • 4Ö0 MHz S^tei^Performance

■ Industry's Lowest Power Consumption

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• Low Static Current

- 1.3-3 mA (1.8V Device Family)

- 11.3-13 mA (2.5V and 3.3V Device Families)

■ Multiple Temperature Range Options

• Commercial: 0 to 70° C T_A (Ambient)

• Industrial: -40 to 85° C T_A (Ambient)

• Automotive: -40 to 125° C T_A (Ambient)

■ Ease of Design

• Excellent First-Time Fit and Refit Capability

• 4 Global Clocks

• 36 Inputs per Logic Block

• Up to 80 Product Terms (PT) per Output

• ORP for Pin Locking

• Density Migration

• Flexible Control, Clocking and OE

• Fast, SpeedLocking™, and Wide PT Paths

• 5V Tolerant Inputs and I/O

■ Easy System Integration

• Operation with 1.8V, 2.5V and 3.3V Supplies

• 1.8V, 2.5V, 3.3V I/O Support

• IEEE 1532 In-System Programmable (ISP™)

• IEEE 1149.1 Boundary Scan Test

• Open Drain Output for Flexible Bus Interface Capability

• Programmable Pull-Up or Bus-Keeper Inputs

• Hot Socketing Capability

• 3.3V PCI Compatible

• Programmable Output Slew Rate

• Lead-free Package Options

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I Logic Block

|Global Routing

I/O Bank

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Logic Block

ispMACH 4000 Product Brief - Lattice Semiconductor - #1

Software, Clock generator, FPGA software, Controller, System-on-chip