ispGDX2 Product Brief - Lattice Semiconductor - #1

The ispGDX2™ family is Lattice's next generation in-system programmable (ISP™) high performance digital crosspoint switch for high-speed bus switching and interfacing with bandwidth of up to 38Gbps. This family combines a flex­ible switching architecture with advanced high speed se­rial I/O (sysHSI™ blocks), sysCLOCK™ PLLs, and sysIO™ interfaces to meet the needs of today's high-speed systems. A multiplexer based architecture and on-chip control logic facilitate the high performance implementation of common switching functions.

ispGDX2 devices are provided in 3.3V, 2.5V or 1.8V core voltage versions and can be programmed in-system via an IEEE 1149.1 interface that is compliant with the IEEE 1532 standard. Voltages required for the I/O buffers are inde­pendent of the core voltage supply. This further enhances the design flexibility of th; family. Typical applications for T the ispGDX.1 include multi-penr mulrpwoce^rOT interfaces"! serial backplanes,'wide dtatsLand/a^Jlress bus multiplexing] programmable control a'gnar^outrflg and programmable bus interfaces.

• 12.8 Gbps (SERDES), 38 Qhp*-(^ithout SERDES)*

• Up to 16 (15X10/FjfFG's for data buffering 1 • High-jpeed ferfarrr/a/ce: f^^=\50 mHz, t_r„ = 3.0ns

• I/O intensive: 6/ td 156 l/ts

• Expanded \X c/pa!bilityYp to^88:l MUX

• Frequency sy^t«esis and skew management

• Clock shifting, multiply and divide capability •Jitter as low as 150ps

• Up to four PLLs

• LVCMOS 1.8, 2.5, 3.3 and LVTTL support

• SSTL 2/3 Class I and II support

• HSTL Class I, III and IV support

• GTL+, PCI-X support

• LVPECL, LVDS and Bus LVDS support

• Hot socketing

• Serializer/de-serializer (SERDES) included

• Built-in Clock Data Recovery (CDR)

• 10B/12B support

- Encoding / decoding

- Sync pattern support

- Symbol alignment

• 8B/10B support

- Sync pattern support

- Symbol alignment

• Source synchronous capability

• IEEE 1532 compliant ISP

• Boundary Scan test through IEEE 1149.1 Interface * Bandwidth assumes 50% of I/Os are inputs and 50% are outputs.

The ispGDX2 family is available in two options. The stan­dard device supports sysHSI capability for ultra fast serial communications and the "E" series, a high performance, low cost device with no sysHSI functionality

Flexible Routing optimized for bus switching

FIFOs for buffering data streams (15x10 bits)

GDX Block includes control logic and data multiplexers

_ sysIO interface for advance

sysHSI Block - two duplex _{standard support}

800 Mbps SERDES