Catalogue - ispClock5300S Product Brief - Lattice Semiconductor

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Clock generator, Gate array, Evaluation kit, Software, Design software

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IN-SYST

ispClock5300S

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Programmable

■Skew &

Integrates Zero Delay Buffers and Fan-out Buffers and Provides Multi-Voltage Logic Interface Vreimination

Imagine using a single, low-cost, programmable clock distribution device as a zero delay buffer (ZDB) or a non-zero delay fan-out buffer (FOB), or both, in the same package instead of selecting different clock ICs from multiple vendors! That is what you get with Lattice's revolutionary ispClock™5300S family.

The ispClock5300S architecture is built around a high performance PLL with programmable input, feedback, and output interface standards. Each output's skew can be individually and precisely controlled to compensate for differences in board trace lengths or timing requirements of the receiving devices. Additionally, each output can be individually configured for fan-out buffer or zero-delay buffer operation. The programmable output termination per output feature enables interfacing of the ispClock5300S device to any clock network with standard trace impedance.

Key Features and Benefits

■ Each Output Programmable as FOB or ZDB from the Reference Clock

• Single chip replaces a variety of ZDB and FOB ICs

• Single chip meets most clock distribution needs

■ Programmable Output Interface Standard

• Integrates logic translation buffers

• Used across multiple clock networks

■ Precision Programmable Skew

• Minimizes serpentine traces to reduce circuit board area

• Compensates for unforeseen changes to set-up and hold times

■ Programmable Output Termination

• Eliminates external termination resistors to reduce circuit board area

■ Programmable Single-ended or Differential Clock Reference Input

• Single chip replaces differential/single-ended input

FOB and ZDB ICs

■ High Performance PLL

• Low jitter (<12ps)

• Low skew (<100ps)

■ JTAG Programming and Boundary Scan

• Increases test coverage and reduces manufacturing

_time

■ Five Devices with 4, 8, 12, 16 or 20 Outputs

• Covers a wide clock distribution application range

Four Modes of Operation

Zero Delay &

Non-Zero Delay Buffer

Non-Zero Delay Buffer with & w/o Divider Mode

Zero Delay Buffer

Single I-

Ended/ ispClock

I 5300S ■ I

Single I ispClock Ended 5300S Clock

Diff.Clock

Single ispClock Ended 5300S Clock Input I

Input

I- -

§ ►

1 ►

External Feedback

Dual Non-Zero Delay Buffer


ispClock 5300S	Output Routing Matrix	_h	Z
ispClock 5300S		—►
w		—►

	Output Routing Matrix
\—	Output Routing Matrix	i

Single Ended Clock -Input

L[v3]-

External Feedback

Single Ended Clock Input

Single Ended Clock

input. jiCT

Single Ended -Clock Input

ispClock5300S Block Diagram

Programmable Clock Input

• Differential/ Single-Ended

• LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL

• Programmable Termination

Skew Control

Output Drivers

REFA/REFP □

REFB/REFN □

REFSEL□

FBKÖ

Programmable Feedback Input PLL Bypass Path for Universal Fan-Out Buffer, Single Ended

LVTTL, LVCMOS, SSTL, HSTL Fan-Out Buffer LVTTL, LVCMOS, SSTL, HSTL, Slew Rate

Programmable Termination Implementation

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ispClock5300S Product Brief - Lattice Semiconductor - #1

Clock generator, Gate array, Evaluation kit, Software, Design software