I0196 ispMACH 4000ZE Product Brief - Lattice Semiconductor - #1

ispMACH 4000ZE

Based on Lattice's popular low power ispMACH® 4000Z family architecture, the second generation ispMACH 4000ZE is ideal for ultra low-power, high-volume portable applications. The ispMACH 4000ZE offers standby current as low as 10uA typical. The cost-optimized and feature-rich ispMACH 4000ZE devices offer ultra-small space-saving csBGA packages, a new Power Guard feature that enables ultra-low system power and new sys­tem integration capabilities including an on-chip user oscillator and timer.

Built on proven E²CMOS® process technology, the ispMACH 4000ZE devices utilize a 1.8V core voltage and provide high levels of functionality and low system power. The ispMACH 4000ZE family supports a wide range of 3.3V, 2.5V and 1.8V I/O standards and features 5V tolerant I/Os when using the LVCMOS 3.3 interface. Additionally, all inputs and I/Os are 5V tolerant.

Versions of the ispMACH 4000ZE family support both com­mercial and industrial temperature grades and are pin compat­ible with the prior zero power ispMACH 4000Z family in like packages.

The new ispMACH 4000ZE family is fully supported by Lattice's easy-to-use and powerful ispLEVER® Classic design software and a wide range of popular third-party tools.

Power Guard lowers standby current in the system by selectively disabling unused input pins. The feature consists of an enabling multiplexer between an I/O pin and input buffer and its associ­ated circuitry inside the device. All I/O pins in a block share a common enable signal or Block Input Enable (BIE) signal. Depending on the device size, there can be from 2 to 16 "blocks" per device. Any I/O pin in the block can be programmed to ignore the BIE signal. The feature can be enabled or disabled on a pin-by-pin basis.

• Standby current as low as 10uA typical

• 1.8Vcoreforlowdynamicpower

• Operates down to 1.6VVcc

• Per pin pull-up, pull-down or bus-keeper control<3HE>

• Power Guard with multiple enable signals <JjE>

• 4.4ns tpD pin-to-pin delay

• 260MHz system performance

• 32 to 256 macrocells

• Multiple temperature range support

- Commercial: 0 to 90°C junction (Tj)

- Industrial: -40 to 105°C junction (Tj)

• Space-saving packages

• Operation with 3.3V, 2.5V, 1.8V or 1.5V LVCMOS I/O

• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces

• Hot-socketing support

• Open-drain output option

• Programmable output slew rate •3.3V PCI compatible

• I/O pins with fast setup path

• Input hysteresis djj>

• IEEE 1149.1 boundary scan testable

• IEEE 1532 ISC compliant

• On-chip user oscillator and timer <3J3>