I0192 LatticeXP2 FPGA Family Product Brief - Lattice Semiconductor - #1

LatticeXP2 Family

LatticeXP2™ devices combine a Look-up Table (LUT) based FPGA fabric with Flash non-volatile cells in an architecture referred to as flexiFLASH™.

The flexiFLASH approach provides a single chip solu­tion with benefits such as instant-on operation, on-chip storage featuring FlashBAK™ embedded block RAM backup, access to general-purpose Serial TAG memory and inherent design security. LatticeXP2 de­vices also support Live Update field reconfiguration with TransFR™, 128-bit AES bitstream encryption and Dual Boot technologies.

The LatticeXP2 FPGA fabric utilizes an underlying LatticeECP2™ architecture that was optimized from the outset with high performance and low cost in mind. LatticeXP2 devices support 4-input LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchro­nous I/O and enhanced sysDSP™ blocks.

Lattice's ispLEVER^® design tool allows complex designs to be efficiently implemented using the

LatticeXP2 family of FPGAs. The ispLEVER tool

is complemented by pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeXP2 family. By using these standardized IP blocks, design­ers are free to concentrate on the unique aspects of their design, increasing their productivity.

■ flexiFLASH Architecture

• Instant-on (lmS), single chip integration

• FlashBAK™ technology

• General-purpose Serial TAG memory

• Design security

■ Live Update Technology

• TransFR™ technology - update logic configuration while equipment continues to operate

• Dual Boot with external SPI Flash improves reliability

• Secure updates with 128 bit AES bitstream encryption

■ Optimized FPGA Architecture

• Densities from 5K to 40K 4-input Look-up Tables (LUTs)

• Up to 885 Kbits sysMEM™ block RAM

• Up to 83 Kbits distributed RAM

• Low cost TQFR PQFP and BGA packaging

■ High Performance sysDSP™ Block

• Three to eight blocks with multiply and accumulate

• 12 to 32 18x18 multipliers

■ Flexible sysIO™ Buffer Supports:

- LVCMOS 3.3/2.5/1.8/1.5/1.2; LVTTL

- SSTL 18 class I, II; SSTL 3/2 class I, II

- HSTL15 class I; HSTL18 class I, II -PCI

- LVDS, Bus-LVDS, LVPECL

■ Pre-engineered Source Synchronous Interfaces

• DDR / DDR2 up to 200MHz/400Mbps

• 7:1 LVDS up to 600Mbps

• Generic up to 750Mbps

■ Up to 4 sysCLOCK™ PLLs

■ Standby Power Reduced by 33%

■ System Level Support

• SPI/JTAG interface for device programming

• IEEE Standard 1149.1 Boundary Scan

• Onboard oscillator for initialization & general use

• Soft Error Detect (SED) logic

• 1.2V power supply core voltage

Live Update via Ethernet ispLeverCORE IP (uP, DDR2, MAC, FIR) I Typical LatticeXP2 Application - Remote Sensor Board M

Pre-engineered Source DSP Functions in Instant-on for Integration Synchronous I/O sysDSP Blocks of Critical Control Logic

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