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| ORMANCE | ||||||||||||
| LatticeECP2/M Family | ||||||||||||
| Exceptional Performance - Uncommon Value The LatticeECP2™ (EConomy Plus 2nd generation) and LatticeECP2M™ families, collectively referred to as LatticeECP2/M, redefine the low-cost FPGA category. By integrating features and capabilities previously available only on higher cost / high performance FPGAs, these families dramatically expand the range of applications that can take advantage of low-cost FPGA products. Features that the LatticeECP2 family brings to the low cost FPGA category include high performance DSP blocks, up to 70K LUT capacity, support for DDR2 memory interfaces at 533Mbps and up to 840Mbps generic LVDS performance. The LatticeECP2 also provides enhanced FPGA configuration options with features such as dual boot, bitstream encryption and TransFR™ I/O capability. The LatticeECP2M includes embedded SERDES, increases density to 95K LUTs at under 0.35W static power, and provides significantly higher memory capacity, up to 5.3Mbits. The SERDES supports many common serial packet protocols including PCI Express and Ethernet (1GbE & SGMII). The LatticeECP2/M devices are an excellent choice for a wide variety of applications, including, low-cost networking, blade servers, network access equipment, consumer electronics, industrial, medical, software defined radio, wireless communications, military and automotive. FPGA Fabric Features and Capabilities ■ Low Cost FPGAs • Features optimized for mainstream applications • Balanced logic-memory-I/O resources ■ Lowest Power SERDES-based FPGA • 95K LUTs with under 0.35W static power ■ Extensive Density and Package Options • 6K to 95K LUT4s, 90 to 583 I/O • Density migration supported • TQFP, PQFP and fpBGA packaging options • Pb-free / RoHS-compliant options ■ Embedded and Distributed Memory • 12K to 202K bits distributed memory • 55K to 5.3M bits sysMEM™ block memory ■ Flexible sysIO™ Buffers • LVCMOS 33/25/18/15/12 •PCI • SSTL3/2/18 & HSTL.15 & HSTL.18 • LVDS, RSDS, Bus-LVDS, MLVDS & LVPECL ■ sysCLOCK™ PLL and DLL • 2 DLLs per device • 2 to 8 PLLs per device ■ System Level Support • IEEE 1149.1 boundary scan • 1.2-volt power supply | ||||||||||||
| LatticeECP2 Features and Benefits EMBEDDED SERDES ■ 3.125Gbps with Low 100mW Power per Channel ■ Receive Equalization and Transmit Pre-emphasis ■ Supports PCI Express, Ethernet (1GbE & SGMI) Plus Multiple Other Standards LOW POWER ■ 95K LUTs with under 0.35W Static Power ■ Improve Thermal Management, System Reliability and Reduce Overall System Cost sysDSP™ BLOCKS ■ Multiply, Accumulate, Addition & Subtraction in Dedicated Blocks ■ Implement High-Performance DSP Functions Such as FIR, FFT and NCO in a Low-Cost FPGA ■ Up to 168 18x18 Multipliers Give 63 GMAC DSP Performance HIGH-SPEED I/O ■ I/O Cells Include Dedicated DDR Mux/Demux, DQS Alignment and Gearbox Logic ■ Pre-Engineered Source Synchronous Interfaces • DDR1 400Mbps; DDR2 533Mbps • SPI4.2 750Mbps • Generic 840Mbps SUPERIOR CONFIGURATION OPTIONS ■ Industry Standard SPI Boot Flash Interface ■ Bitstream Encryption Prevents Design Piracy ■ Dual Boot Provides Backup Configuration Copy ■ TransFR I/O Supports Updates While System Operates | ||||||||||||
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