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| : ORM A I | 1GRAMMABLE SYST | ||||||||||||||||||||||||
| E A I ni | |||||||||||||||||||||||||
| LatticeSC FPGA Family | |||||||||||||||||||||||||
| Innovation, Integration, and PURESPEED™ The LatticeSC™ (System Chip) family of FPGAs combines a high-performance FPGA fabric, 3.8Gbps SERDES and PCS, high-performance I/Os, large embedded RAM, and embedded ASIC blocks in a single industry-leading architecture. This FPGA family is fabricated on a state-of-the-art Fujitsu 90nm technology to provide the highest performance FPGA in the industry. This family of devices includes specific features to meet the needs of today's high-speed connectivity-based system designs. These features include SERDES, the industry's most advanced embedded PCS (Physical Coding sub-layer), up to 7.8Mb of Embedded Block RAM (EBR), and dedicated I/O logic to support source synchronous I/O standards such as RapidIO, HyperTransport™, SPI4.2, SFI4, and XGMII. A plethora of hierarchical clock routing and clock management resources are provided to support the precise programmable logic timing needed in today's high-end system designs. High-speed I/O with bandwidths up to 2Gbps per pin make this family ideal for high throughput systems. And for low-cost system-level integration, the LatticeSC family offers up to 12 embedded structured ASIC blocks per device with a variety of pre-engineered IP blocks. | |||||||||||||||||||||||||
| Key Features and Benefits ■ High Performance FPGA Fabric • Industry's fastest FPGA core performance • 15K to 115K four-input Look-up Tables (LUT4s) • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks ■ High Speed SERDES and flexiPCS™ • 4 to 32 SERDES per device @ 600Mbps to 3.8Gbps • Tx pre-emphasis and Rx equalization • Low power (105mW per channel) • Embedded Physical Coding Sublayer (PCS) supports: PCI Express, GbE, XAUI, SONET, and other packet protocols ■ PURESPEED™ Technology: 2Gbps Parallel I/O • Input Delay (INDEL) and Adaptive Input Logic (AIL) dynamically aligns data for robust high performance source synchronous I/O support • Supports generic DDR up to 2Gbps; generic SDR up to lGbps; DDR memories up to 800Mbps • Comprehensive standards support: LVCMOS, LVTTL, PCI, PCI-X, LVDS, HyperTransport, HSTL, SSTL, with programmable On Die Termination (ODT) options ■ Memory Intensive FPGA • 1Mb to 7.8Mb Embedded Block RAM @ 500MHz • Additional Distributed RAM: 240K to 1.8Mbits sysCLOCK™ PLLs and DLLs • Eight PLLs per device and twelve DLLs per device • Spread spectrum support on PLLs ■ Masked Array for Cost Optimization (MACO) • On-chip structured ASIC blocks provide pre-engineered IP at lower power and cost ■ System Level Support • IEEE Standard 1149.1 boundary scan • IEEE Standard 1532 in-system configuration • Embedded PowerPC microprocessor interface • Embedded system bus | |||||||||||||||||||||||||
| High-Speed Connectivity Solutions BACKPLANE / HIGH SPEED SERIAL Integrated high-speed SERDES Supports SONET, GbE, XAUI, PCI Express, Fibre Channel, SFI-5 and more More SERDES channels for greater flexibility and easier customization CHIP-TO-CHIP / CHIP-TO-MEMORY Lattice PURESPEED I/O technology enables connectivity to virtually any digital device Each PURESPEED I/O buffer supports up to 2Gbps | |||||||||||||||||||||||||
| Supports parallel I/O standards, from | Digital IC | ||||||||||||||||||||||||
| 2Gbps LVDS to PCI/PCI-X Dedicated interface logic seamlessly handles SDR/DDR/QDR memories | |||||||||||||||||||||||||
| NETWORKING DATAPATH ■ Ideal for bridging ASSPs ■ LatticeSC devices include: high-speed logic, embedded RAM, fast clocking schemes, and ample routing for maximum utilization | |||||||||||||||||||||||||
| MORE OF THE BEST | |||||||||||||||||||||||||