6 pages in the catalogue
I0181F LatticeSC FPGA Family Product Brief |
|
I0181F LatticeSC FPGA Family Product Brief p 1
: ORM A I 1GRAMMABLE SYST E A I ni LatticeSC FPGA Family Innovation, Integration, and PURESPEED™ The LatticeSC™ (System Chip) family of FPGAs combines a high-performance FPGA fabric, 3.8G... |
|
I0181F LatticeSC FPGA Family Product Brief p 2
LatticeSC Architecture Architecture Overview The LatticeSC family of FPGAs combines a high-performance FPGA fabric, high-speed SERDES, structured ASIC blocks, high-performance I/Os and large embedded... |
|
I0181F LatticeSC FPGA Family Product Brief p 3
SERDES and flexiPCS Lattice pioneered the concept of combining SERDES and optimized PCS on a programmable device. ■ Up to 32 Channels per Device ■ Speeds from 600Mbps up to 3.8Gbps σ... |
|
I0181F LatticeSC FPGA Family Product Brief p 4
MACO Masked Array for Cost Reduction MACO Overview Think of MACO blocks as structured ASICs embedded in an FPGA fabric. MACO technology is based on a unique library of cells created with Fujitsu's 90... |
|
I0181F LatticeSC FPGA Family Product Brief p 5
MACO Blocks in Detail flexiMAC Protocol Engine - Configurable at design time for: "I I Status/Byte Counters ) Microcoded State Machine Ethernet ■ 1GbE or 10GbE MAC Function ■ Flexible Pac... |
